Fix spelling

2026-08-28 17:14:11 +02:00 · 2019-04-23 08:58:34 -07:00
parent c84cdc711c
commit f66792c43a
1 changed files with 1 additions and 1 deletions
@@ -370,7 +370,7 @@ Verilog Attributes and non-standard features

 - When defining a macro with `define, all text between triple double quotes
  is interpreted as macro body, even if it contains unescaped newlines. The
-  tipple double quotes are removed from the macro body. For example:
+  triple double quotes are removed from the macro body. For example:

      `define MY_MACRO(a, b) """
         assign a = 23;