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passes: trivial twine damage

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This commit is contained in:
Emil J. Tywoniak
2026-10-02 18:42:01 +02:00
parent 19b0c694ea
commit f4a2982445
72 changed files with 443 additions and 389 deletions
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passes/cmds/autoname.cc
+13 -11
View File
@@ -91,7 +91,7 @@ struct node {
// Is this name final?
bool decided = false;
const IdString& name() const { return cell ? cell->name : wire->name; }
IdString name() const { return cell ? IdString(cell->name) : IdString(wire->name); }
};
// Decides the order of exploring neighbors
@@ -158,12 +158,11 @@ struct ModuleAutonamer
// Resolve selection before renaming
for (auto &nd : nodes) {
IdString name = nd.name();
nd.selected = nd.cell ? module->selected(nd.cell) : module->selected(nd.wire);
nd.is_public = (name[0] != '$');
nd.is_public = nd.name().isPublic();
nd.renameable = !nd.is_public && (nd.cell || nd.wire->port_id == 0);
if (nd.is_public)
nd.name_length = name.str().size();
nd.name_length = module->design->twines.str(nd.name()).size();
}
// Only possible once every fanout is known
@@ -177,9 +176,10 @@ struct ModuleAutonamer
node &nd = nodes[to];
if (!nd.renameable || nd.decided)
return;
std::string port = module->design->twines.unescaped_str(edge.port);
string suffix = nd.cell
? stringf("_%s_%s", nd.cell->type.unescape(), edge.port.unescape())
: stringf("_%s", edge.port.unescape());
? stringf("_%s_%s", nd.cell->type.unescape(), port)
: stringf("_%s", port);
cost c{edge.score, nodes[from].name_length + suffix.length(), edge_pos};
if (c >= nd.c)
return;
@@ -222,8 +222,10 @@ struct ModuleAutonamer
void append_name(int n, string &out)
{
const node &nd = nodes[n];
if (nd.is_public || nd.selected)
return nd.name().append_to(&out);
if (nd.is_public || nd.selected) {
out += module->design->twines.str(nd.name());
return;
}
append_name(nd.from_node, out);
out += nd.suffix;
}
@@ -237,12 +239,12 @@ struct ModuleAutonamer
full.reserve(nd.name_length);
append_name(nd.from_node, full);
full += nd.suffix;
IdString name = module->uniquify(IdString(full));
IdString name = module->uniquify(full);
if (nd.cell) {
log_debug("Rename cell %s in %s to %s.\n", nd.cell, module, name.unescape());
log_debug("Rename cell %s in %s to %s.\n", nd.cell, module, PooledName(module, name).unescape());
module->rename(nd.cell, name);
} else {
log_debug("Rename wire %s in %s to %s.\n", nd.wire, module, name.unescape());
log_debug("Rename wire %s in %s to %s.\n", nd.wire, module, PooledName(module, name).unescape());
module->rename(nd.wire, name);
}
renamed++;
passes/cmds/bugpoint.cc
+9 -9
View File
@@ -183,7 +183,7 @@ struct BugpointPass : public Pass {
RTLIL::Design *design_copy = new RTLIL::Design;
for (auto module : design->modules())
design_copy->add(module->clone());
module->clone(design_copy);
Pass::call(design_copy, "proc_clean -quiet");
Pass::call(design_copy, "clean -purge");
@@ -196,7 +196,7 @@ struct BugpointPass : public Pass {
{
RTLIL::Design *design_copy = new RTLIL::Design;
for (auto module : design->modules())
design_copy->add(module->clone());
module->clone(design_copy);
int index = 0;
if (modules)
@@ -296,7 +296,7 @@ struct BugpointPass : public Pass {
if (index++ == seed)
{
log_header(design, "Trying to remove cell port %s.%s.%s.\n", mod, cell, it.first.unescape());
log_header(design, "Trying to remove cell port %s.%s.%s.\n", mod, cell, PooledName(design_copy, it.first).unescape());
RTLIL::SigSpec port_x(State::Sx, port.size());
cell->unsetPort(it.first);
cell->setPort(it.first, port_x);
@@ -305,7 +305,7 @@ struct BugpointPass : public Pass {
if (!stage2 && (cell->input(it.first) || cell->output(it.first)) && index++ == seed)
{
log_header(design, "Trying to expose cell port %s.%s.%s as module port.\n", mod, cell, it.first.unescape());
log_header(design, "Trying to expose cell port %s.%s.%s as module port.\n", mod, cell, PooledName(design_copy, it.first).unescape());
RTLIL::Wire *wire = mod->addWire(NEW_ID, port.size());
wire->set_bool_attribute(ID($bugpoint));
wire->port_input = cell->input(it.first);
@@ -334,7 +334,7 @@ struct BugpointPass : public Pass {
if (index++ == seed)
{
log_header(design, "Trying to remove process %s.%s.\n", mod, process.first.unescape());
log_header(design, "Trying to remove process %s.%s.\n", mod, PooledName(design_copy, process.first).unescape());
removed_process = process.second;
break;
}
@@ -363,7 +363,7 @@ struct BugpointPass : public Pass {
{
if (index++ == seed)
{
log_header(design, "Trying to remove assign %s %s in %s.%s.\n", log_signal(it->first), log_signal(it->second), mod, pr.first.unescape());
log_header(design, "Trying to remove assign %s %s in %s.%s.\n", log_signal(it->first), log_signal(it->second), mod, PooledName(design_copy, pr.first).unescape());
cs->actions.erase(it);
return design_copy;
}
@@ -389,7 +389,7 @@ struct BugpointPass : public Pass {
{
if (index++ == seed)
{
log_header(design, "Trying to remove sync %s update %s %s in %s.%s.\n", log_signal(sy->signal), log_signal(it->first), log_signal(it->second), mod, pr.first.unescape());
log_header(design, "Trying to remove sync %s update %s %s in %s.%s.\n", log_signal(sy->signal), log_signal(it->first), log_signal(it->second), mod, PooledName(design_copy, pr.first).unescape());
sy->actions.erase(it);
return design_copy;
}
@@ -399,7 +399,7 @@ struct BugpointPass : public Pass {
{
if (index++ == seed)
{
log_header(design, "Trying to remove sync %s memwr %s %s %s %s in %s.%s.\n", log_signal(sy->signal), it->memid.unescape(), log_signal(it->address), log_signal(it->data), log_signal(it->enable), mod, pr.first.unescape());
log_header(design, "Trying to remove sync %s memwr %s %s %s %s in %s.%s.\n", log_signal(sy->signal), PooledName(design_copy, it->memid).unescape(), log_signal(it->address), log_signal(it->data), log_signal(it->enable), mod, PooledName(design_copy, pr.first).unescape());
sy->mem_write_actions.erase(it);
// Remove the bit for removed action from other actions' priority masks.
for (auto it2 = sy->mem_write_actions.begin(); it2 != sy->mem_write_actions.end(); ++it2) {
@@ -678,7 +678,7 @@ struct BugpointPass : public Pass {
Pass::call(design, "design -reset");
crashing_design = clean_design(crashing_design, clean, /*do_delete=*/true);
for (auto module : crashing_design->modules())
design->add(module->clone());
module->clone(design);
delete crashing_design;
}
passes/cmds/check.cc
+11 -11
View File
@@ -169,7 +169,7 @@ struct CheckPass : public Pass {
for (auto bit : sigmap(action.first)) {
wire_drivers[bit].push_back(
stringf("action %s <= %s (case rule) in process %s",
log_signal(action.first), log_signal(action.second), proc_it.first.unescape()));
log_signal(action.first), log_signal(action.second), module->design->twines.unescaped_str(proc_it.first).c_str()));
if (bit.wire)
proc_driven_bits.insert(bit);
}
@@ -193,7 +193,7 @@ struct CheckPass : public Pass {
for (auto bit : sigmap(action.first)) {
wire_drivers[bit].push_back(
stringf("action %s <= %s (sync rule) in process %s",
log_signal(action.first), log_signal(action.second), proc_it.first.unescape()));
log_signal(action.first), log_signal(action.second), module->design->twines.unescaped_str(proc_it.first).c_str()));
if (bit.wire && sync->type != RTLIL::SyncType::STi)
proc_driven_bits.insert(bit);
}
@@ -231,7 +231,7 @@ struct CheckPass : public Pass {
SigBit to = sigmap(to_portsig[to_bit]);
if (from.wire && to.wire)
topo.edge(std::make_pair(from.wire->name, from.offset), std::make_pair(to.wire->name, to.offset));
topo.edge(std::make_pair(IdString(from.wire->name), from.offset), std::make_pair(IdString(to.wire->name), to.offset));
}
bool detail_costly(Cell *cell) {
@@ -281,14 +281,14 @@ struct CheckPass : public Pass {
if (cell->input(conn.first))
for (auto bit : sigmap(conn.second))
if (bit.wire)
topo.edge(std::make_pair(bit.wire->name, bit.offset),
std::make_pair(cell->name, -1));
topo.edge(std::make_pair(IdString(bit.wire->name), bit.offset),
std::make_pair(IdString(cell->name), -1));
if (cell->output(conn.first))
for (auto bit : sigmap(conn.second))
if (bit.wire)
topo.edge(std::make_pair(cell->name, -1),
std::make_pair(bit.wire->name, bit.offset));
topo.edge(std::make_pair(IdString(cell->name), -1),
std::make_pair(IdString(bit.wire->name), bit.offset));
}
// Return false to signify the fallback
@@ -335,7 +335,7 @@ struct CheckPass : public Pass {
if (output && !input && bit.wire)
wire_drivers_count[bit]++;
if (output && (bit.wire || !input))
wire_drivers[bit].push_back(stringf("port %s[%d] of cell %s (%s)", conn.first.unescape(), i,
wire_drivers[bit].push_back(stringf("port %s[%d] of cell %s (%s)", cell->module->design->twines.unescaped_str(conn.first).c_str(), i,
cell, cell->type.unescape()));
if (output)
driver_cells[bit] = cell;
@@ -436,8 +436,8 @@ struct CheckPass : public Pass {
SigBit edge_to = sigmap(cell->getPort(to_port))[to_bit];
if (edge_from == from && edge_to == to && nhits++ < HITS_LIMIT)
message += stringf(" %s[%d] --> %s[%d]\n", from_port.unescape(), from_bit,
to_port.unescape(), to_bit);
message += stringf(" %s[%d] --> %s[%d]\n", cell->module->design->twines.unescaped_str(from_port).c_str(), from_bit,
cell->module->design->twines.unescaped_str(to_port).c_str(), to_bit);
if (nhits == HITS_LIMIT)
message += " ...\n";
}
@@ -445,7 +445,7 @@ struct CheckPass : public Pass {
Wire *wire = module->wire(pair.first);
log_assert(wire);
SigBit bit(module->wire(pair.first), pair.second);
SigBit bit(wire, pair.second);
log_assert(driver_cells.count(bit));
Cell *driver = driver_cells.at(bit);
passes/cmds/edgetypes.cc
+4 -4
View File
@@ -92,12 +92,12 @@ struct EdgetypePass : public Pass {
auto sink_bit_index = std::get<2>(sink);
string source_str = multibit_ports.count(std::pair<IdString, IdString>(source_cell_type, source_port_name)) ?
stringf("%s.%s[%d]", source_cell_type.unescape(), source_port_name.unescape(), source_bit_index) :
stringf("%s.%s", source_cell_type.unescape(), source_port_name.unescape());
stringf("%s.%s[%d]", PooledName(module, source_cell_type).unescape(), PooledName(module, source_port_name).unescape(), source_bit_index) :
stringf("%s.%s", PooledName(module, source_cell_type).unescape(), PooledName(module, source_port_name).unescape());
string sink_str = multibit_ports.count(std::pair<IdString, IdString>(sink_cell_type, sink_port_name)) ?
stringf("%s.%s[%d]", sink_cell_type.unescape(), sink_port_name.unescape(), sink_bit_index) :
stringf("%s.%s", sink_cell_type.unescape(), sink_port_name.unescape());
stringf("%s.%s[%d]", PooledName(module, sink_cell_type).unescape(), PooledName(module, sink_port_name).unescape(), sink_bit_index) :
stringf("%s.%s", PooledName(module, sink_cell_type).unescape(), PooledName(module, sink_port_name).unescape());
edge_cache.insert(source_str + " " + sink_str);
}
passes/cmds/example_dt.cc
+28 -17
View File
@@ -43,6 +43,17 @@ struct ExampleDtPass : public Pass
ExampleWorker worker(module);
DriverMap dm;
TwinePool &twines = design->twines;
const IdString fn_concat = twines.add(std::string("$$concat"));
const IdString fn_input = twines.add(std::string("$$input"));
const IdString fn_buf = twines.add(std::string("$$buf"));
const IdString fn_slice = twines.add(std::string("$$slice"));
const IdString fn_state = twines.add(std::string("$$state"));
const IdString fn_cell_output = twines.add(std::string("$$cell_output"));
const IdString fn_const = twines.add(std::string("$$const"));
const IdString fn_multi = twines.add(std::string("$$multi"));
const IdString fn_undriven = twines.add(std::string("$$undriven"));
struct ExampleFn {
IdString name;
dict<IdString, Const> parameters;
@@ -99,7 +110,7 @@ struct ExampleDtPass : public Pass
ExampleGraph::Ref node = compute_graph[i];
if (spec.chunks().size() > 1) {
node.set_function(ID($$concat));
node.set_function(fn_concat);
for (auto const &chunk : spec.chunks()) {
node.append_arg(enqueue(chunk));
@@ -111,16 +122,16 @@ struct ExampleDtPass : public Pass
if (wire_chunk.is_whole()) {
node.sparse_attr() = wire_chunk.wire->name;
if (wire_chunk.wire->port_input) {
node.set_function(ExampleFn(ID($$input), {{wire_chunk.wire->name, {}}}));
node.set_function(ExampleFn(fn_input, {{wire_chunk.wire->name, {}}}));
} else {
DriveSpec driver = dm(DriveSpec(wire_chunk));
node.set_function(ID($$buf));
node.set_function(fn_buf);
node.append_arg(enqueue(driver));
}
} else {
DriveChunkWire whole_wire(wire_chunk.wire, 0, wire_chunk.wire->width);
node.set_function(ExampleFn(ID($$slice), {{ID(offset), wire_chunk.offset}, {ID(width), wire_chunk.width}}));
node.set_function(ExampleFn(fn_slice, {{ID::offset, wire_chunk.offset}, {ID::width, wire_chunk.width}}));
node.append_arg(enqueue(whole_wire));
}
} else if (chunk.is_port()) {
@@ -130,7 +141,7 @@ struct ExampleDtPass : public Pass
if (port_chunk.cell->type.in(ID($dff), ID($ff)))
{
Cell *cell = port_chunk.cell;
node.set_function(ExampleFn(ID($$state), {{cell->name, {}}}));
node.set_function(ExampleFn(fn_state, {{cell->name, {}}}));
for (auto const &conn : cell->connections()) {
if (!dm.celltypes.cell_input(cell->type, conn.first))
continue;
@@ -139,11 +150,11 @@ struct ExampleDtPass : public Pass
}
else
{
node.set_function(ExampleFn(ID($$cell_output), {{port_chunk.port, {}}}));
node.set_function(ExampleFn(fn_cell_output, {{port_chunk.port, {}}}));
node.append_arg(enqueue(DriveBitMarker(cells(port_chunk.cell), 0)));
}
} else {
node.set_function(ID($$buf));
node.set_function(fn_buf);
DriveSpec driver = dm(DriveSpec(port_chunk));
node.append_arg(enqueue(driver));
@@ -151,14 +162,14 @@ struct ExampleDtPass : public Pass
} else {
DriveChunkPort whole_port(port_chunk.cell, port_chunk.port, 0, GetSize(port_chunk.cell->connections().at(port_chunk.port)));
node.set_function(ExampleFn(ID($$slice), {{ID(offset), port_chunk.offset}}));
node.set_function(ExampleFn(fn_slice, {{ID::offset, port_chunk.offset}}));
node.append_arg(enqueue(whole_port));
}
} else if (chunk.is_constant()) {
node.set_function(ExampleFn(ID($$const), {{ID(value), chunk.constant()}}));
node.set_function(ExampleFn(fn_const, {{ID::value, chunk.constant()}}));
} else if (chunk.is_multiple()) {
node.set_function(ID($$multi));
node.set_function(fn_multi);
for (auto const &driver : chunk.multiple().multiple())
node.append_arg(enqueue(driver));
} else if (chunk.is_marker()) {
@@ -172,7 +183,7 @@ struct ExampleDtPass : public Pass
node.append_arg(enqueue(DriveChunkPort(cell, conn)));
}
} else if (chunk.is_none()) {
node.set_function(ID($$undriven));
node.set_function(fn_undriven);
} else {
log_error("unhandled drivespec: %s\n", log_signal(chunk));
@@ -208,7 +219,7 @@ struct ExampleDtPass : public Pass
for (int i = 0; i < compute_graph.size(); ++i)
{
if (compute_graph[i].function().name == ID($$buf) && !compute_graph[i].has_sparse_attr() && compute_graph[i].arg(0).index() < i)
if (compute_graph[i].function().name == fn_buf && !compute_graph[i].has_sparse_attr() && compute_graph[i].arg(0).index() < i)
{
alias.push_back(alias[compute_graph[i].arg(0).index()]);
@@ -226,13 +237,13 @@ struct ExampleDtPass : public Pass
{
auto ref = compute_graph[i];
log("n%d ", i);
log("%s", ref.function().name.unescape());
log("%s", PooledName(design, ref.function().name).unescape());
for (auto const &param : ref.function().parameters)
{
if (param.second.empty())
log("[%s]", param.first.unescape());
log("[%s]", PooledName(design, param.first).unescape());
else
log("[%s=%s]", param.first.unescape(), log_const(param.second));
log("[%s=%s]", PooledName(design, param.first).unescape(), log_const(param.second));
}
log("(");
@@ -244,13 +255,13 @@ struct ExampleDtPass : public Pass
}
log(")\n");
if (ref.has_sparse_attr())
log("// wire %s\n", ref.sparse_attr().unescape());
log("// wire %s\n", PooledName(design, ref.sparse_attr()).unescape());
log("// was #%d %s\n", ref.attr(), log_signal(queue[ref.attr()]));
}
for (auto const &key : compute_graph.keys())
{
log("return %d as %s \n", key.second, key.first.unescape());
log("return %d as %s \n", key.second, PooledName(design, key.first).unescape());
}
}
log("Plugin test passed!\n");
passes/cmds/icell_liberty.cc
+13 -11
View File
@@ -50,7 +50,7 @@ struct LibertyStubber {
auto base_name = base->name.str().substr(1);
auto derived_name = derived->name.str().substr(1);
FfTypeData ffType(base_name);
FfTypeData ffType(base->name);
LibertyItemizer i(f);
if (ffType.has_gclk) {
@@ -63,18 +63,18 @@ struct LibertyStubber {
}
f << "\tcell (\"" << derived_name << "\") {\n";
auto& base_type = ct.cell_types[base_name];
auto& base_type = ct.cell_types[base->name];
i.indent = 3;
auto sorted_ports = derived->ports;
// Hack for CLK and C coming before Q does
auto cmp = [](IdString l, IdString r) { return l.str() < r.str(); };
auto cmp = [derived](IdString l, IdString r) { return derived->design->twines.str(l) < derived->design->twines.str(r); };
std::sort(sorted_ports.begin(), sorted_ports.end(), cmp);
std::string clock_pin_name = "";
for (auto x : sorted_ports) {
std::string port_name = x.unescape();
std::string port_name = derived->design->twines.unescaped_str(x);
bool is_input = base_type.inputs.count(x);
bool is_output = base_type.outputs.count(x);
f << "\t\tpin (" << x.unescape() << ") {\n";
f << "\t\tpin (" << port_name << ") {\n";
if (is_input && !is_output) {
i.item("direction", "input");
} else if (!is_input && is_output) {
@@ -119,20 +119,21 @@ struct LibertyStubber {
{
auto base_name = base->name.str().substr(1);
auto derived_name = derived->name.str().substr(1);
if (!ct.cell_types.count(base_name)) {
if (!ct.cell_types.count(base->name)) {
log_debug("skip skeleton for %s\n", base_name.c_str());
return;
}
if (StaticCellTypes::categories.is_ff(base_name))
if (StaticCellTypes::categories.is_ff(base->name))
return liberty_flop(base, derived, f);
auto& base_type = ct.cell_types[base_name];
auto& base_type = ct.cell_types[base->name];
f << "\tcell (\"" << derived_name << "\") {\n";
for (auto x : derived->ports) {
std::string port_name = derived->design->twines.unescaped_str(x);
bool is_input = base_type.inputs.count(x);
bool is_output = base_type.outputs.count(x);
f << "\t\tpin (" << x.unescape() << ") {\n";
f << "\t\tpin (" << port_name << ") {\n";
if (is_input && !is_output) {
f << "\t\t\tdirection : input;\n";
} else if (!is_input && is_output) {
@@ -193,9 +194,10 @@ struct IcellLiberty : Pass {
if (!inst_module || !inst_module->get_blackbox_attribute())
continue;
Module *base = inst_module;
if (!done.count(base->name)) {
IdString base_name_id = base->name;
if (!done.count(base_name_id)) {
stubber.liberty_cell(base, base, *liberty_file);
done.insert(base->name);
done.insert(base_name_id);
}
}
}
passes/cmds/printattrs.cc
+5 -5
View File
@@ -45,7 +45,7 @@ struct PrintAttrsPass : public Pass {
return stringf("%*s", indent, "");
}
static void log_const(RTLIL::IdString s, const RTLIL::Const &x, const unsigned int indent) {
static void log_const(PooledName s, const RTLIL::Const &x, const unsigned int indent) {
if (x.flags & RTLIL::CONST_FLAG_STRING)
log("%s(* %s=\"%s\" *)\n", get_indent_str(indent), s.unescape(), x.decode_string());
else if (x.flags == RTLIL::CONST_FLAG_NONE || x.flags == RTLIL::CONST_FLAG_SIGNED)
@@ -63,17 +63,17 @@ struct PrintAttrsPass : public Pass {
for (auto mod : design->selected_modules())
{
if (design->selected_whole_module(mod)) {
log("%s%s\n", get_indent_str(indent), mod->name.unescape());
log("%s%s\n", get_indent_str(indent), mod);
indent += 2;
for (auto &it : mod->attributes)
log_const(it.first, it.second, indent);
log_const(PooledName(design, it.first), it.second, indent);
}
for (auto cell : mod->selected_cells()) {
log("%s%s\n", get_indent_str(indent), cell->name.unescape());
indent += 2;
for (auto &it : cell->attributes)
log_const(it.first, it.second, indent);
log_const(PooledName(design, it.first), it.second, indent);
indent -= 2;
}
@@ -81,7 +81,7 @@ struct PrintAttrsPass : public Pass {
log("%s%s\n", get_indent_str(indent), wire->name.unescape());
indent += 2;
for (auto &it : wire->attributes)
log_const(it.first, it.second, indent);
log_const(PooledName(design, it.first), it.second, indent);
indent -= 2;
}
passes/cmds/scc.cc
+1 -1
View File
@@ -356,7 +356,7 @@ struct SccPass : public Pass {
{
for (auto attr : setAttr)
{
IdString attr_name(RTLIL::escape_id(attr.first));
IdString attr_name = design->twines.add(RTLIL::escape_id(attr.first));
string attr_valstr = attr.second;
string index = stringf("%d", scc_counter);
passes/cmds/sdc/sdc.cc
+3 -3
View File
@@ -151,7 +151,7 @@ struct SdcObjects {
design_cells.push_back(std::make_pair(path, cell));
for (auto& pin : cell->connections()) {
IdString pin_name = pin.first;
std::string pin_name_sdc = path + "/" + pin.first.str().substr(1);
std::string pin_name_sdc = path + "/" + design->twines.str(pin.first);
design_pins.push_back(std::make_pair(pin_name_sdc, std::make_pair(cell, pin_name)));
}
if (auto sub_mod = mod->design->module(cell->type)) {
@@ -169,9 +169,9 @@ struct SdcObjects {
RTLIL::Wire *wire = top->wire(port);
if (!wire) {
// This should not be possible. See https://github.com/YosysHQ/yosys/pull/5594#issue-3791198573
log_error("Port %s doesn't exist", port.unescape());
log_error("Port %s doesn't exist", PooledName(design, port).unescape());
}
design_ports.push_back(std::make_pair(port.str().substr(1), wire));
design_ports.push_back(std::make_pair(design->twines.str(port), wire));
}
std::list<std::string> hierarchy{};
sniff_module(hierarchy, top);
passes/cmds/setundef.cc
+6 -4
View File
@@ -39,7 +39,9 @@ static RTLIL::Wire * add_wire(RTLIL::Module *module, std::string name, int width
RTLIL::Wire *wire = NULL;
name = RTLIL::escape_id(name);
if (module->count_id(name) != 0)
IdString t = module->design->twines.add(name);
if (module->count_id(t) != 0)
{
log("Module %s already has such an object %s.\n", module->name, name);
name += "$";
@@ -424,7 +426,7 @@ struct SetundefPass : public Pass {
{
for (auto wire : module->wires())
{
if (wire->name[0] == (wire_types ? '\\' : '$'))
if (wire->name.isPublic() == wire_types)
continue;
if (!wire->attributes.count(ID::init))
@@ -453,7 +455,7 @@ struct SetundefPass : public Pass {
{
for (auto wire : module->wires())
{
if (wire->name[0] == (wire_types ? '\\' : '$'))
if (wire->name.isPublic() == wire_types)
continue;
for (auto bit : sigmap(wire))
@@ -474,7 +476,7 @@ struct SetundefPass : public Pass {
{
for (auto wire : module->wires())
{
if (wire->name[0] == (wire_types ? '\\' : '$'))
if (wire->name.isPublic() == wire_types)
continue;
for (auto bit : sigmap(wire))
passes/cmds/splice.cc
+2 -2
View File
@@ -319,12 +319,12 @@ struct SplicePass : public Pass {
continue;
}
if (args[argidx] == "-port" && argidx+1 < args.size()) {
ports.insert(RTLIL::escape_id(args[++argidx]));
ports.insert(design->twines.add(RTLIL::escape_id(args[++argidx])));
no_outputs = true;
continue;
}
if (args[argidx] == "-no_port" && argidx+1 < args.size()) {
no_ports.insert(RTLIL::escape_id(args[++argidx]));
no_ports.insert(design->twines.add(RTLIL::escape_id(args[++argidx])));
continue;
}
break;
passes/cmds/splitcells.cc
+13 -10
View File
@@ -61,14 +61,14 @@ struct SplitcellsWorker
SigBit bit(sig[i]);
if (!bit_drivers_db.count(bit)) continue;
bit_users_db[bit].insert(tuple<IdString,IdString,int>(wire->name,
IdString(), i-std::get<2>(bit_drivers_db[bit])));
IdString::Null, i-std::get<2>(bit_drivers_db[bit])));
}
}
}
int split(Cell *cell, const std::string &format)
{
if (cell->type.in("$and", "$mux", "$not", "$or", "$pmux", "$xnor", "$xor"))
if (cell->type.in(ID($and), ID($mux), ID($not), ID($or), ID($pmux), ID($xnor), ID($xor)))
{
SigSpec outsig = sigmap(cell->getPort(ID::Y));
if (GetSize(outsig) <= 1) return 0;
@@ -95,9 +95,10 @@ struct SplitcellsWorker
int slice_msb = slices[i]-1;
int slice_lsb = slices[i-1];
IdString slice_name = module->uniquify(cell->name.str() + (slice_msb == slice_lsb ?
std::string s = cell->name.str() + (slice_msb == slice_lsb ?
stringf("%c%d%c", format[0], slice_lsb, format[1]) :
stringf("%c%d%c%d%c", format[0], slice_msb, format[2], slice_lsb, format[1])));
stringf("%c%d%c%d%c", format[0], slice_msb, format[2], slice_lsb, format[1]));
IdString slice_name = module->uniquify(std::move(s));
Cell *slice = module->addCell(slice_name, cell);
@@ -126,15 +127,15 @@ struct SplitcellsWorker
if (slice->hasParam(ID::WIDTH))
slice->setParam(ID::WIDTH, GetSize(slice->getPort(ID::Y)));
log(" slice %d: %s => %s\n", i, slice_name, log_signal(slice->getPort(ID::Y)));
log(" slice %d: %s => %s\n", i, module->design->twines.str(slice_name).c_str(), log_signal(slice->getPort(ID::Y)));
}
module->remove(cell);
return GetSize(slices)-1;
}
if (cell->type.in("$ff", "$dff", "$dffe", "$dffsr", "$dffsre", "$adff", "$adffe", "$aldff", "$aldffe",
"$sdff", "$sdffce", "$sdffe", "$dlatch", "$dlatchsr", "$adlatch"))
if (cell->type.in(ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($aldff), ID($aldffe),
ID($sdff), ID($sdffce), ID($sdffe), ID($dlatch), ID($dlatchsr), ID($adlatch)))
{
auto splitports = {ID::D, ID::Q, ID::AD, ID::SET, ID::CLR};
auto splitparams = {ID::ARST_VALUE, ID::SRST_VALUE};
@@ -161,9 +162,11 @@ struct SplitcellsWorker
int slice_msb = slices[i]-1;
int slice_lsb = slices[i-1];
IdString slice_name = module->uniquify(cell->name.str() + (slice_msb == slice_lsb ?
TwinePool &twines = module->design->twines;
std::string s = cell->name.str() + (slice_msb == slice_lsb ?
stringf("%c%d%c", format[0], slice_lsb, format[1]) :
stringf("%c%d%c%d%c", format[0], slice_msb, format[2], slice_lsb, format[1])));
stringf("%c%d%c%d%c", format[0], slice_msb, format[2], slice_lsb, format[1]));
IdString slice_name = module->uniquify(std::move(s));
Cell *slice = module->addCell(slice_name, cell);
@@ -185,7 +188,7 @@ struct SplitcellsWorker
slice->setParam(ID::WIDTH, GetSize(slice->getPort(ID::Q)));
log(" slice %d: %s => %s\n", i, slice_name.unescape(), log_signal(slice->getPort(ID::Q)));
log(" slice %d: %s => %s\n", i, twines.unescaped_str(slice_name), log_signal(slice->getPort(ID::Q)));
}
module->remove(cell);
passes/cmds/sta.cc
+2 -2
View File
@@ -206,7 +206,7 @@ struct StaWorker
log("Latest arrival time in '%s' is %d:\n", module, maxarrival);
auto it = endpoints.find(maxbit);
if (it != endpoints.end() && it->second.sink)
log(" %6d %s (%s.%s)\n", maxarrival, it->second.sink, it->second.sink->type.unescape(), it->second.port.unescape());
log(" %6d %s (%s.%s)\n", maxarrival, it->second.sink, it->second.sink->type.unescape(), PooledName(it->second.sink->module, it->second.port).unescape());
else {
log(" %6d (%s)\n", maxarrival, b.wire->port_output ? "<primary output>" : "<unknown>");
if (!b.wire->port_output)
@@ -217,7 +217,7 @@ struct StaWorker
int arrival = b.wire->get_intvec_attribute(ID::sta_arrival)[b.offset];
if (jt->second.driver) {
log(" %s\n", log_signal(b));
log(" %6d %s (%s.%s->%s)\n", arrival, jt->second.driver, jt->second.driver->type.unescape(), jt->second.src_port.unescape(), jt->second.dst_port.unescape());
log(" %6d %s (%s.%s->%s)\n", arrival, jt->second.driver, jt->second.driver->type.unescape(), PooledName(jt->second.driver->module, jt->second.src_port).unescape(), PooledName(jt->second.driver->module, jt->second.dst_port).unescape());
}
else if (b.wire->port_input)
log(" %6d %s (%s)\n", arrival, log_signal(b), "<primary input>");
passes/cmds/test_select.cc
+2 -1
View File
@@ -1,3 +1,4 @@
#include "kernel/rtlil.h"
#include "kernel/yosys.h"
USING_YOSYS_NAMESPACE
@@ -147,7 +148,7 @@ struct TestSelectPass : public Pass {
log_debug(" Adding %s.\n", mod);
selected_modules.insert(mod->name);
} else for (auto *memb : mod->selected_members()) {
log_debug(" Adding %s.%s.\n", mod, memb);
log_debug(" Adding %s.%s.\n", mod, mod->design->obj_name(memb).c_str());
selected_members[mod->name].insert(memb);
}
}
passes/cmds/torder.cc
+6 -6
View File
@@ -59,8 +59,8 @@ struct TorderPass : public Pass {
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
if (args[argidx] == "-stop" && argidx+2 < args.size()) {
IdString cell_type = RTLIL::escape_id(args[++argidx]);
IdString cell_port = RTLIL::escape_id(args[++argidx]);
IdString cell_type = design->twines.add(RTLIL::escape_id(args[++argidx]));
IdString cell_port = design->twines.add(RTLIL::escape_id(args[++argidx]));
stop_db[cell_type].insert(cell_port);
continue;
}
@@ -78,12 +78,12 @@ struct TorderPass : public Pass {
SigMap sigmap(module);
dict<SigBit, pool<IdString>> bit_drivers, bit_users;
TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
TopoSort<IdString> toposort;
for (auto cell : module->selected_cells())
for (auto conn : cell->connections())
{
if (stop_db.count(cell->type) && stop_db.at(cell->type).count(conn.first))
if (stop_db.count(IdString(cell->type)) && stop_db.at(IdString(cell->type)).count(conn.first))
continue;
if (!noautostop && yosys_celltypes.cell_known(cell->type)) {
@@ -116,12 +116,12 @@ struct TorderPass : public Pass {
for (auto &it : toposort.loops) {
log(" loop");
for (auto cell : it)
log(" %s", cell);
log(" %s", design->twines.str(cell));
log("\n");
}
for (auto cell : toposort.sorted)
log(" cell %s\n", cell);
log(" cell %s\n", design->twines.str(cell));
}
}
} TorderPass;
passes/cmds/trace.cc
+1 -1
View File
@@ -38,7 +38,7 @@ struct TraceMonitor : public RTLIL::Monitor
void notify_connect(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
{
log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", cell->module, cell, port.unescape(), log_signal(sig), log_signal(old_sig));
log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", cell->module, cell, PooledName(cell->module, port).unescape(), log_signal(sig), log_signal(old_sig));
}
void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) override
passes/cmds/viz.cc
+6 -6
View File
@@ -703,13 +703,13 @@ struct VizWorker
void update_attrs()
{
IdString vg_id("\\vg");
IdString vg_id = module->design->twines.add(std::string("\\vg"));
for (auto c : module->cells())
c->attributes.erase(vg_id);
for (auto g : graph.nodes) {
for (auto name : g->names()) {
auto w = module->wire(name);
auto c = module->cell(name);
for (auto ref : g->names()) {
auto w = module->wire(ref);
auto c = module->cell(ref);
if (w) w->attributes[vg_id] = g->index;
if (c) c->attributes[vg_id] = g->index;
}
@@ -734,7 +734,7 @@ struct VizWorker
buffer.emplace_back();
for (auto name : g->names())
buffer.back().push_back(name.unescape());
buffer.back().push_back(module->design->twines.unescaped_str(name));
std::sort(buffer.back().begin(), buffer.back().end());
std::sort(buffer.begin(), buffer.end());
@@ -782,7 +782,7 @@ struct VizWorker
g->names().sort();
std::string label; // = stringf("vg=%d\\n", g->index);
for (auto n : g->names())
label = label + (label.empty() ? "" : "\\n") + n.unescape();
label = label + (label.empty() ? "" : "\\n") + PooledName(module, n).unescape();
fprintf(f, "\tn%d [shape=rectangle,label=\"%s\"];\n", g->index, label.c_str());
} else {
std::string label = stringf("vg=%d | %d cells", g->index, GetSize(g->names()));
passes/cmds/xprop.cc
+19 -18
View File
@@ -264,7 +264,7 @@ struct XpropWorker
auto not_0 = module->Not(NEW_ID, result.is_0);
auto not_1 = module->Not(NEW_ID, result.is_1);
auto not_x = module->Not(NEW_ID, result.is_x);
auto valid = module->ReduceAnd(NEW_ID, {
auto valid = module->ReduceAnd(NEW_ID, SigSpec{
module->Eq(NEW_ID, result.is_0, module->And(NEW_ID, not_1, not_x)),
module->Eq(NEW_ID, result.is_1, module->And(NEW_ID, not_0, not_x)),
module->Eq(NEW_ID, result.is_x, module->And(NEW_ID, not_0, not_1)),
@@ -274,7 +274,7 @@ struct XpropWorker
else
module->addAssume(NEW_ID_SUFFIX("xprop_enc"), valid, State::S1);
if (options.debug_asserts) {
auto bad_bits = module->Bweqx(NEW_ID, {result.is_0, result.is_1, result.is_x}, Const(State::Sx, GetSize(result) * 3));
auto bad_bits = module->Bweqx(NEW_ID, SigSpec{result.is_0, result.is_1, result.is_x}, Const(State::Sx, GetSize(result) * 3));
module->addAssert(NEW_ID_SUFFIX("xprop_debug"), module->LogicNot(NEW_ID, bad_bits), State::S1);
}
}
@@ -486,9 +486,9 @@ struct XpropWorker
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto name = cell->name;
std::string name_str = cell->name.str();
module->remove(cell);
module->addXnor(name, sig_a, sig_b, sig_y);
module->addXnor(name_str, sig_a, sig_b, sig_y);
return;
}
@@ -497,13 +497,13 @@ struct XpropWorker
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto name = cell->name;
auto type = cell->type;
std::string name_str = cell->name.str();
IdString type = cell->type;
module->remove(cell);
if (type == ID($eqx))
module->addEq(name, sig_a, sig_b, sig_y);
module->addEq(name_str, sig_a, sig_b, sig_y);
else
module->addNe(name, sig_a, sig_b, sig_y);
module->addNe(name_str, sig_a, sig_b, sig_y);
return;
}
@@ -685,7 +685,7 @@ struct XpropWorker
auto delta_0 = module->Xnor(NEW_ID, enc_a.is_0, enc_b.is_0);
auto delta_1 = module->Xnor(NEW_ID, enc_a.is_1, enc_b.is_1);
auto eq = module->ReduceAnd(NEW_ID, {delta_0, delta_1});
auto eq = module->ReduceAnd(NEW_ID, SigSpec{delta_0, delta_1});
auto res = cell->type == ID($nex) ? module->Not(NEW_ID, eq) : eq;
@@ -749,7 +749,7 @@ struct XpropWorker
int width = GetSize(enc_y);
auto all_x = module->ReduceOr(NEW_ID, {
auto all_x = module->ReduceOr(NEW_ID, SigSpec{
enc_s.is_x,
module->And(NEW_ID, enc_s.is_1, module->Sub(NEW_ID, enc_s.is_1, Const(1, width)))
});
@@ -787,7 +787,7 @@ struct XpropWorker
SigSpec y_1 = module->addWire(NEW_ID, GetSize(sig_y));
SigSpec y_x = module->addWire(NEW_ID, GetSize(sig_y));
auto encoded_type = cell->type == ID($shiftx) ? ID($shift) : cell->type;
IdString encoded_type = cell->type == ID($shiftx) ? IdString{ID($shift)} : cell->type;
if (cell->type == ID($shiftx)) {
std::swap(enc_a.is_0, enc_a.is_x);
@@ -892,7 +892,7 @@ struct XpropWorker
ff.val_init = init_q_is_1;
ff.emit();
ff.name = NEW_ID;
ff.name = module->design->twines.add(NEW_ID);
ff.cell = nullptr;
ff.sig_d = enc_d.is_x;
ff.sig_q = enc_q.is_x;
@@ -982,8 +982,8 @@ struct XpropWorker
if (wire->port_input == wire->port_output) {
log_warning("Port %s not an input or an output port which is not supported by xprop\n", wire);
} else if ((options.split_inputs && !options.assume_def_inputs && wire->port_input) || (options.split_outputs && wire->port_output)) {
auto port_d = module->uniquify(stringf("%s_d", port));
auto port_x = module->uniquify(stringf("%s_x", port));
auto port_d = module->uniquify(module->design->twines.str(port) + "_d");
auto port_x = module->uniquify(module->design->twines.str(port) + "_x");
auto wire_d = module->addWire(port_d, GetSize(wire));
auto wire_x = module->addWire(port_x, GetSize(wire));
@@ -1003,7 +1003,7 @@ struct XpropWorker
if (options.split_public) {
// Need to hide the original wire so split_public doesn't try to split it again
module->rename(wire, NEW_ID_SUFFIX(wire->name.c_str()));
module->rename(wire, NEW_ID_SUFFIX(wire->name.str()));
}
} else {
auto enc = encoded(wire, true);
@@ -1035,8 +1035,9 @@ struct XpropWorker
continue;
int index_d = 0;
int index_x = 0;
auto name_d = module->uniquify(stringf("%s_d", wire->name), index_d);
auto name_x = module->uniquify(stringf("%s_x", wire->name), index_x);
std::string wname = wire->name.str();
auto name_d = module->uniquify(wname + "_d", index_d);
auto name_x = module->uniquify(wname + "_x", index_x);
auto hdlname = wire->get_hdlname_attribute();
@@ -1056,7 +1057,7 @@ struct XpropWorker
module->connect(wire_d, enc.is_1);
module->connect(wire_x, enc.is_x);
module->rename(wire, NEW_ID_SUFFIX(wire->name.c_str()));
module->rename(wire, NEW_ID_SUFFIX(wire->name.str()));
}
}
passes/equiv/equiv_add.cc
+3 -2
View File
@@ -56,8 +56,9 @@ struct EquivAddPass : public Pass {
if (GetSize(args) == 4 && args[1] == "-cell")
{
Cell *gold_cell = module->cell(RTLIL::escape_id(args[2]));
Cell *gate_cell = module->cell(RTLIL::escape_id(args[3]));
TwineSearch search(&module->design->twines);
Cell *gold_cell = module->cell(search.find(RTLIL::escape_id(args[2])));
Cell *gate_cell = module->cell(search.find(RTLIL::escape_id(args[3])));
if (gold_cell == nullptr) {
if (try_mode) {
passes/equiv/equiv_miter.cc
+4 -5
View File
@@ -143,8 +143,7 @@ struct EquivMiterWorker
for (auto w : miter_wires)
miter_module->addWire(w->name, w->width);
for (auto c : miter_cells) {
miter_module->addCell(c->name, c);
auto mc = miter_module->cell(c->name);
auto mc = miter_module->addCell(c->name, c);
for (auto &conn : mc->connections())
mc->setPort(conn.first, sigmap(conn.second));
}
@@ -242,7 +241,7 @@ struct EquivMiterWorker
}
if (mode_trigger) {
auto w = miter_module->addWire(ID(trigger));
auto w = miter_module->addWire("trigger");
w->port_output = true;
miter_module->addReduceOr(NEW_ID, trigger_signals, w);
}
@@ -316,11 +315,11 @@ struct EquivMiterPass : public Pass {
if (argidx >= args.size())
log_cmd_error("Invalid number of arguments.\n");
worker.miter_name = RTLIL::escape_id(args[argidx++]);
worker.miter_name = design->twines.add(RTLIL::escape_id(args[argidx++]));
extra_args(args, argidx, design);
if (design->module(worker.miter_name))
log_cmd_error("Miter module %s already exists.\n", worker.miter_name.unescape());
log_cmd_error("Miter module %s already exists.\n", PooledName(design, worker.miter_name).unescape());
worker.source_module = nullptr;
for (auto m : design->selected_modules()) {
passes/equiv/equiv_purge.cc
+6 -6
View File
@@ -37,7 +37,7 @@ struct EquivPurgeWorker
Wire *wire = sig.as_wire();
if (wire->name.isPublic()) {
if (!wire->port_output) {
log(" Module output: %s (%s)\n", log_signal(wire), cellname.unescape());
log(" Module output: %s (%s)\n", log_signal(wire), PooledName(module->design, cellname).unescape());
wire->port_output = true;
}
return wire;
@@ -46,14 +46,14 @@ struct EquivPurgeWorker
while (1)
{
IdString name = stringf("\\equiv_%d", name_cnt++);
if (module->count_id(name))
std::string name = stringf("\\equiv_%d", name_cnt++);
if (module->count_id(module->design->twines.find(name)))
continue;
Wire *wire = module->addWire(name, GetSize(sig));
wire->port_output = true;
module->connect(wire, sig);
log(" Module output: %s (%s)\n", log_signal(wire), cellname.unescape());
log(" Module output: %s (%s)\n", log_signal(wire), PooledName(module->design, cellname).unescape());
return wire;
}
}
@@ -73,8 +73,8 @@ struct EquivPurgeWorker
while (1)
{
IdString name = stringf("\\equiv_%d", name_cnt++);
if (module->count_id(name))
std::string name = stringf("\\equiv_%d", name_cnt++);
if (module->count_id(module->design->twines.find(name)))
continue;
Wire *wire = module->addWire(name, GetSize(sig));
passes/fsm/fsm_export.cc
+2 -2
View File
@@ -69,8 +69,8 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st
log("\n");
log("Exporting FSM `%s' from module `%s' to file `%s'.\n",
cell->name.c_str(),
module->name.c_str(),
cell->name,
module->name,
kiss_name.c_str());
kiss_file.open(kiss_name, std::ios::out | std::ios::trunc);
passes/hierarchy/hierarchy.cc
+1 -1
View File
@@ -389,7 +389,7 @@ RTLIL::Module *get_module(RTLIL::Design &design,
if (cell_type[0] == '$') {
if (check && !yosys_celltypes.cell_known(cell.type))
log_error("Cell type `%s' referenced in module `%s' in cell `%s' is neither a known internal cell type nor part of the design.\n",
cell_type.c_str(), parent.name.c_str(), cell.name.c_str());
cell_type.c_str(), parent.name, cell.name);
return nullptr;
}
passes/hierarchy/submod.cc
+14 -12
View File
@@ -115,12 +115,10 @@ struct SubmodWorker
}
}
RTLIL::Module *new_mod = new RTLIL::Module;
new_mod->name = submod.full_name;
design->add(new_mod);
RTLIL::Module *new_mod = design->addModule(submod.full_name);
int auto_name_counter = 1;
std::set<RTLIL::IdString> all_wire_names;
std::set<std::string> all_wire_names;
for (auto &it : wire_flags) {
all_wire_names.insert(it.first->name);
}
@@ -221,7 +219,8 @@ struct SubmodWorker
submod.cells.clear();
if (!copy_mode) {
RTLIL::Cell *new_cell = module->addCell(submod.full_name, submod.full_name);
IdString submod_type = design->twines.add(std::string{submod.full_name});
RTLIL::Cell *new_cell = module->addCell(submod.full_name, submod_type);
for (auto &it : wire_flags)
{
RTLIL::SigSpec old_sig = sigmap(it.first);
@@ -289,9 +288,10 @@ struct SubmodWorker
if (submodules.count(submod_str) == 0) {
submodules[submod_str].name = submod_str;
submodules[submod_str].full_name = module->name.str() + "_" + submod_str;
while (design->module(submodules[submod_str].full_name) != nullptr ||
module->count_id(submodules[submod_str].full_name) != 0)
std::string module_name_str(module->name.str());
submodules[submod_str].full_name = module_name_str + "_" + submod_str;
while (design->module(design->twines.add(std::string{submodules[submod_str].full_name})) != nullptr ||
module->count_id(design->twines.add(std::string{submodules[submod_str].full_name})) != 0)
submodules[submod_str].full_name += "_";
}
@@ -389,10 +389,12 @@ struct SubmodPass : public Pass {
bool did_something = true;
while (did_something) {
did_something = false;
std::vector<RTLIL::IdString> queued_modules;
for (auto mod : design->modules())
if (handled_modules.count(mod->name) == 0 && design->selected_whole_module(mod->name))
queued_modules.push_back(mod->name);
std::vector<IdString> queued_modules;
for (auto mod : design->modules()) {
IdString mod_name = mod->name;
if (handled_modules.count(mod_name) == 0 && design->selected_whole_module(mod))
queued_modules.push_back(mod_name);
}
for (auto &modname : queued_modules)
if (design->module(modname) != nullptr) {
SubmodWorker worker(design, design->module(modname), copy_mode, hidden_mode);
passes/memory/memlib.cc
+3 -3
View File
@@ -94,7 +94,7 @@ struct ResourceDef {
};
struct RamDef {
IdString id;
std::string id;
dict<std::string, pool<Const>> opts;
RamKind kind;
Caps<Empty> forbid;
@@ -185,12 +185,12 @@ struct Parser {
}
}
IdString get_id() {
std::string get_id() {
std::string token = get_token();
if (token.empty() || (token[0] != '$' && token[0] != '\\')) {
log_error("%s:%d: expected id string, got `%s`.\n", filename, line_number, token);
}
return IdString(token);
return token;
}
std::string get_name() {
passes/memory/memlib.h
+1 -1
View File
@@ -140,7 +140,7 @@ struct RamClock {
};
struct Ram {
IdString id;
std::string id;
RamKind kind;
dict<std::string, Const> options;
std::vector<PortGroup> port_groups;
passes/memory/memory_memx.cc
+1 -1
View File
@@ -42,7 +42,7 @@ struct MemoryMemxPass : public Pass {
addr.extend_u0(32);
SigSpec res = mem.module->Nex(NEW_ID, mem.module->ReduceXor(NEW_ID, addr), mem.module->ReduceXor(NEW_ID, {addr, State::S1}));
SigSpec res = mem.module->Nex(NEW_ID, mem.module->ReduceXor(NEW_ID, addr), mem.module->ReduceXor(NEW_ID, SigSpec{addr, State::S1}));
if (start_addr != 0)
res = mem.module->LogicAnd(NEW_ID, res, mem.module->Ge(NEW_ID, addr, start_addr));
res = mem.module->LogicAnd(NEW_ID, res, mem.module->Lt(NEW_ID, addr, end_addr));
passes/memory/memory_share.cc
+3 -3
View File
@@ -80,7 +80,7 @@ struct MemoryShareWorker
if (GetSize(mem.rd_ports) <= 1)
return false;
log("Consolidating read ports of memory %s.%s by address:\n", module, mem.memid.unescape());
log("Consolidating read ports of memory %s.%s by address:\n", module, PooledName(module, mem.memid).unescape());
bool changed = false;
int abits = 0;
@@ -197,7 +197,7 @@ struct MemoryShareWorker
if (GetSize(mem.wr_ports) <= 1)
return false;
log("Consolidating write ports of memory %s.%s by address:\n", module, mem.memid.unescape());
log("Consolidating write ports of memory %s.%s by address:\n", module, PooledName(module, mem.memid).unescape());
bool changed = false;
int abits = 0;
@@ -316,7 +316,7 @@ struct MemoryShareWorker
if (eligible_ports.size() <= 1)
return;
log("Consolidating write ports of memory %s.%s using sat-based resource sharing:\n", module, mem.memid.unescape());
log("Consolidating write ports of memory %s.%s using sat-based resource sharing:\n", module, PooledName(module, mem.memid).unescape());
// Group eligible ports by clock domain and width.
passes/opt/dff/eqbits.cc
+1 -1
View File
@@ -308,7 +308,7 @@ struct EqBitsContext
void drop_all_classes(EqCandidates &cand)
{
log("opt_dff -sat: skipping all equivalent-flip-flop merges in module %s (solver effort budget "
"exhausted before the equivalences could be proven).\n", log_id(worker.module));
"exhausted before the equivalences could be proven).\n", worker.module);
cand.classes.clear();
}
passes/opt/dff/opt_dff.h
+1 -1
View File
@@ -69,7 +69,7 @@ struct OptDffWorker
if (!sat_warned)
log_warning("opt_dff -sat: solver effort budget for module %s is exhausted, leaving the "
"remaining FFs un-optimized. Raise or clear the limit with the scratchpad "
"option 'opt_dff.sat_effort' (0 disables it).\n", log_id(module));
"option 'opt_dff.sat_effort' (0 disables it).\n", module);
sat_warned = true;
return true;
}
passes/opt/opt_balance_tree.cc
+1 -1
View File
@@ -404,7 +404,7 @@ struct OptBalanceTreePass : public Pass {
// Log stats
for (auto cell_type : cell_types)
log("Converted %d %s cells into trees.\n", cell_count[cell_type], cell_type.unescape());
log("Converted %d %s cells into trees.\n", cell_count[cell_type], PooledName(design, cell_type).unescape());
// Clean up
Yosys::run_pass("clean -purge");
passes/opt/opt_hier.cc
+2 -2
View File
@@ -101,7 +101,7 @@ struct ModuleIndex {
if (!port || (!port->port_input && !port->port_output) || port->width != value.size()) {
log_error("Port %s connected on instance %s not found in module %s"
" or width is not matching\n",
port_name.unescape(), instantiation, module);
PooledName(module, port_name).unescape(), instantiation, module);
}
if (port->port_input && port->port_output) {
@@ -290,7 +290,7 @@ struct UsageData {
if (!port || (!port->port_input && !port->port_output) || port->width != value.size()) {
log_error("Port %s connected on instance %s not found in module %s"
" or width is not matching\n",
port_name.unescape(), instance, module);
PooledName(module, port_name).unescape(), instance, module);
}
if (port->port_input && port->port_output) {
passes/opt/opt_lut.cc
+2 -2
View File
@@ -99,7 +99,7 @@ struct OptLutWorker
}
for (int i = 0; i < GetSize(dlogic); i++)
{
log(" with %-12s (#%d) %4d\n", dlogic[i].cell_type, i, dlogic_counts[i]);
log(" with %-12s (#%d) %4d\n", module->design->twines.str(dlogic[i].cell_type), i, dlogic_counts[i]);
}
}
@@ -174,7 +174,7 @@ struct OptLutWorker
if (sigmap(lut_input[dlogic_conn.first]) != sigmap(lut_dlogic.second->getPort(dlogic_conn.second)[0]))
{
log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type, module, lut_dlogic.second);
log_debug(" LUT input A[%d] (wire %s) not connected to %s port %s (wire %s).\n", dlogic_conn.first, log_signal(lut_input[dlogic_conn.first]), lut_dlogic.second->type, dlogic_conn.second, log_signal(lut_dlogic.second->getPort(dlogic_conn.second)));
log_debug(" LUT input A[%d] (wire %s) not connected to %s port %s (wire %s).\n", dlogic_conn.first, log_signal(lut_input[dlogic_conn.first]), lut_dlogic.second->type, module->design->twines.str(dlogic_conn.second).c_str(), log_signal(lut_dlogic.second->getPort(dlogic_conn.second)));
legal = false;
break;
}
passes/opt/opt_mem.cc
+3 -3
View File
@@ -108,13 +108,13 @@ struct OptMemPass : public Pass {
}
State bit;
if (!always_0[i]) {
log("%s.%s: removing const-1 lane %d\n", module->name.unescape(), mem.memid.unescape(), i);
log("%s.%s: removing const-1 lane %d\n", module->name.unescape(), PooledName(module, mem.memid).unescape(), i);
bit = State::S1;
} else if (!always_1[i]) {
log("%s.%s: removing const-0 lane %d\n", module->name.unescape(), mem.memid.unescape(), i);
log("%s.%s: removing const-0 lane %d\n", module->name.unescape(), PooledName(module, mem.memid).unescape(), i);
bit = State::S0;
} else {
log("%s.%s: removing const-x lane %d\n", module->name.unescape(), mem.memid.unescape(), i);
log("%s.%s: removing const-x lane %d\n", module->name.unescape(), PooledName(module, mem.memid).unescape(), i);
bit = State::Sx;
}
// Reconnect read port data.
passes/opt/opt_mem_feedback.cc
+2 -2
View File
@@ -163,7 +163,7 @@ struct OptMemFeedbackWorker
{
auto &port = mem.wr_ports[i];
log(" Analyzing %s.%s write port %d.\n", module, mem.memid.unescape(), i);
log(" Analyzing %s.%s write port %d.\n", module, PooledName(module, mem.memid).unescape(), i);
for (int sub = 0; sub < (1 << port.wide_log2); sub++)
{
@@ -232,7 +232,7 @@ struct OptMemFeedbackWorker
// Okay, let's do it.
log("Populating enable bits on write ports of memory %s.%s with async read feedback:\n", module, mem.memid.unescape());
log("Populating enable bits on write ports of memory %s.%s with async read feedback:\n", module, PooledName(module, mem.memid).unescape());
// If a write port has a feedback path that we're about to bypass,
// but also has priority over some other write port, the feedback
passes/opt/opt_mem_widen.cc
+1 -1
View File
@@ -65,7 +65,7 @@ struct OptMemWidenPass : public Pass {
factor_log2 = port.wide_log2;
if (factor_log2 == 0)
continue;
log("Widening base width of memory %s in module %s by factor %d.\n", mem.memid.unescape(), module->name.unescape(), 1 << factor_log2);
log("Widening base width of memory %s in module %s by factor %d.\n", PooledName(module, mem.memid).unescape(), module->name.unescape(), 1 << factor_log2);
total_count++;
// The inits are too messy to expand one-by-one, for they may
// collide with one another after expansion. Just hit it with
passes/opt/opt_merge.cc
+1 -1
View File
@@ -459,7 +459,7 @@ struct OptMergeWorker
for (auto &it : remove_cell->connections()) {
if (remove_cell->output(it.first)) {
RTLIL::SigSpec keep_sig = keep_cell->getPort(it.first);
log_debug(" Redirecting output %s: %s = %s\n", it.first,
log_debug(" Redirecting output %s: %s = %s\n", module->design->twines.str(it.first),
log_signal(it.second), log_signal(keep_sig));
Const init = initvals(keep_sig);
initvals.remove_init(it.second);
passes/opt/opt_muxtree.cc
+2 -2
View File
@@ -299,7 +299,7 @@ struct OptMuxtreeWorker
live_ports.push_back(port_idx);
} else {
log(" dead port %d/%d on %s %s.\n", port_idx+1, GetSize(mi.ports),
mi.cell->type.c_str(), mi.cell->name.c_str());
mi.cell->type, mi.cell->name);
removed_count++;
}
}
@@ -534,7 +534,7 @@ struct OptMuxtreeWorker
}
if (did_something) {
log(" Replacing known input bits on port %s of cell %s: %s -> %s\n", portname.unescape(),
log(" Replacing known input bits on port %s of cell %s: %s -> %s\n", PooledName(design, portname).unescape(),
muxinfo.cell, log_signal(muxinfo.cell->getPort(portname)), log_signal(sig));
muxinfo.cell->setPort(portname, sig);
}
passes/opt/rmports.cc
+2 -2
View File
@@ -169,7 +169,7 @@ struct RmportsPassPass : public Pass {
for(auto p : ports_to_remove)
{
log(" Removing port \"%s\" from instance \"%s\"\n",
p.c_str(), cell->type.c_str());
module->design->twines.str(p), cell->type.str());
cell->unsetPort(p);
}
}
@@ -259,7 +259,7 @@ struct RmportsPassPass : public Pass {
// Print the ports out as we go through them
for(auto port : unused_ports)
{
log(" removing unused port %s\n", port);
log(" removing unused port %s\n", module->design->twines.str(port));
removed_ports[module->name].insert(port);
// Remove from ports list
passes/opt/share.cc
+1 -1
View File
@@ -1208,7 +1208,7 @@ struct ShareWorker
if (!sat_warned)
log_warning("share: solver effort budget for module %s is exhausted, leaving the "
"remaining cells un-shared. Raise or clear the limit with the scratchpad "
"option 'share.sat_effort' (0 disables it).\n", log_id(module));
"option 'share.sat_effort' (0 disables it).\n", module);
sat_warned = true;
return true;
}
passes/pmgen/pmgen.py
+4 -4
View File
@@ -417,9 +417,9 @@ with open(outfile, "w") as f:
for v, n in sorted(ids.items()):
if n[0] == "\\":
print(" IdString {}{{\"\\{}\"}};".format(v, n), file=f)
print(" IdString {}{{ID::{}}};".format(v, n[1:]), file=f)
else:
print(" IdString {}{{\"{}\"}};".format(v, n), file=f)
print(" IdString {}{{ID::{}}};".format(v, n), file=f)
print("", file=f)
print(" void add_siguser(const SigSpec &sig, Cell *cell) {", file=f)
@@ -454,7 +454,7 @@ with open(outfile, "w") as f:
print(" SigSpec port(Cell *cell, IdString portname) {", file=f)
print(" try {", file=f)
print(" return sigmap(cell->getPort(portname));", file=f)
print(" } catch(std::out_of_range&) { log_error(\"Accessing non existing port %s\\n\",portname); }", file=f)
print(" } catch(std::out_of_range&) { log_error(\"Accessing non existing port %s\\n\", cell->module->design->twines.str(portname).c_str()); }", file=f)
print(" }", file=f)
print("", file=f)
print(" SigSpec port(Cell *cell, IdString portname, const SigSpec& defval) {", file=f)
@@ -465,7 +465,7 @@ with open(outfile, "w") as f:
print(" Const param(Cell *cell, IdString paramname) {", file=f)
print(" try {", file=f)
print(" return cell->getParam(paramname);", file=f)
print(" } catch(std::out_of_range&) { log_error(\"Accessing non existing parameter %s\\n\",paramname); }", file=f)
print(" } catch(std::out_of_range&) { log_error(\"Accessing non existing parameter %s\\n\", PooledName(module, paramname).unescape()); }", file=f)
print(" }", file=f)
print("", file=f)
print(" Const param(Cell *cell, IdString paramname, const Const& defval) {", file=f)
passes/proc/proc_dff.cc
+2 -2
View File
@@ -85,7 +85,7 @@ void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec
cell->attributes = proc->attributes;
log(" created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n",
cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
cell->type, cell->name, clk_polarity ? "positive" : "negative");
}
void gen_aldff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_out,
@@ -154,7 +154,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
break;
log("Creating register for signal `%s.%s' using process `%s.%s'.\n",
mod->name.c_str(), log_signal(sig), mod->name.c_str(), proc->name.c_str());
mod->name, log_signal(sig), mod->name, proc->name);
RTLIL::SigSpec insig = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
RTLIL::SyncRule *sync_edge = NULL;
passes/proc/proc_dlatch.cc
+9 -9
View File
@@ -299,7 +299,7 @@ struct proc_dlatch_db_t
for (int i = 0; i < (is_bwmux ? 1 : GetSize(sig_s)); i++) {
n = find_mux_constant(sig_b[i*width + index], needle, set_undef);
if (n != false_node) {
if (set_undef && sig_b[i*width + index] == SigBit(needle)) {
if (set_undef && sig_b[i*width + index] == needle) {
SigSpec sig = cell->getPort(ID::B);
sig[i*width + index] = State::Sx;
cell->setPort(ID::B, sig);
@@ -448,7 +448,7 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc, LatchPolicy policy)
if (proc->get_bool_attribute(ID::always_ff))
log_error("Found non edge/level sensitive event in always_ff process `%s.%s'.\n",
db.module->name.c_str(), proc->name.c_str());
db.module->name, proc->name);
for (auto ss : sr->actions)
{
@@ -508,10 +508,10 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc, LatchPolicy policy)
if (proc->get_bool_attribute(ID::always_latch) && !is_nosync)
log_error("No latch inferred for signal `%s.%s' from always_latch process `%s.%s'.\n",
db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str());
db.module->name, log_signal(lhs), db.module->name, proc->name);
else if (!is_nosync)
log("No latch inferred for signal `%s.%s' from process `%s.%s'.\n",
db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str());
db.module->name, log_signal(lhs), db.module->name, proc->name);
for (auto &bit : lhs) {
State val = db.initvals(bit);
if (db.initvals(bit) != State::Sx) {
@@ -563,19 +563,19 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc, LatchPolicy policy)
if (proc->get_bool_attribute(ID::always_comb))
log_error("Latch inferred for signal `%s.%s' from always_comb process `%s.%s'.\n",
db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str());
db.module->name, log_signal(lhs), db.module->name, proc->name);
else if (proc->get_bool_attribute(ID::always_latch))
log("Latch inferred for signal `%s.%s' from always_latch process `%s.%s': %s\n",
db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), cell);
db.module->name, log_signal(lhs), db.module->name, proc->name, cell);
else if (policy == LatchPolicy::Error)
log_error("Latch inferred for signal `%s.%s' from process `%s.%s': %s\n",
db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), cell);
db.module->name, log_signal(lhs), db.module->name, proc->name, cell);
else if (policy == LatchPolicy::Warn)
log_warning("Latch inferred for signal `%s.%s' from process `%s.%s': %s\n",
db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), cell);
db.module->name, log_signal(lhs), db.module->name, proc->name, cell);
else
log("Latch inferred for signal `%s.%s' from process `%s.%s': %s\n",
db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), cell);
db.module->name, log_signal(lhs), db.module->name, proc->name, cell);
}
offset += width;
passes/sat/clk2fflogic.cc
+10 -8
View File
@@ -90,7 +90,7 @@ struct Clk2fflogicPass : public Pass {
module->addFfGate(NEW_ID, sig, sampled_sig);
else
module->addFf(NEW_ID, sig, sampled_sig);
return module->Eqx(NEW_ID, {sampled_sig, sig}, polarity ? SigSpec {State::S0, State::S1} : SigSpec {State::S1, State::S0});
return module->Eqx(NEW_ID, SigSpec{sampled_sig, sig}, polarity ? SigSpec {State::S0, State::S1} : SigSpec {State::S1, State::S0});
}
// Sampled and current value of a data signal.
SampledSig sample_data(Module *module, SigSpec sig, RTLIL::Const init, bool is_fine, bool set_attribute = false) {
@@ -169,11 +169,13 @@ struct Clk2fflogicPass : public Pass {
for (auto &mem : Mem::get_selected_memories(module))
{
std::string memid = mem.memid.unescape();
for (int i = 0; i < GetSize(mem.rd_ports); i++) {
auto &port = mem.rd_ports[i];
if (port.clk_enable)
log_error("Read port %d of memory %s.%s is clocked. This is not supported by \"clk2fflogic\"! "
"Call \"memory\" with -nordff to avoid this error.\n", i, mem.memid.unescape(), module);
"Call \"memory\" with -nordff to avoid this error.\n", i, memid, module);
}
for (int i = 0; i < GetSize(mem.wr_ports); i++)
@@ -184,10 +186,10 @@ struct Clk2fflogicPass : public Pass {
continue;
log("Modifying write port %d on memory %s.%s: CLK=%s, A=%s, D=%s\n",
i, module, mem.memid.unescape(), log_signal(port.clk),
i, module, memid, log_signal(port.clk),
log_signal(port.addr), log_signal(port.data));
Wire *past_clk = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#past_clk#%s", mem.memid.unescape(), i, log_signal(port.clk))));
Wire *past_clk = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#past_clk#%s", memid, i, log_signal(port.clk))));
past_clk->attributes[ID::init] = port.clk_polarity ? State::S1 : State::S0;
module->addFf(NEW_ID, port.clk, past_clk);
@@ -201,15 +203,15 @@ struct Clk2fflogicPass : public Pass {
clock_edge_pattern.append(State::S0);
}
SigSpec clock_edge = module->Eqx(NEW_ID, {port.clk, SigSpec(past_clk)}, clock_edge_pattern);
SigSpec clock_edge = module->Eqx(NEW_ID, SigSpec{port.clk, SigSpec(past_clk)}, clock_edge_pattern);
SigSpec en_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#en_q", mem.memid.unescape(), i)), GetSize(port.en));
SigSpec en_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#en_q", memid, i)), GetSize(port.en));
module->addFf(NEW_ID, port.en, en_q);
SigSpec addr_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#addr_q", mem.memid.unescape(), i)), GetSize(port.addr));
SigSpec addr_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#addr_q", memid, i)), GetSize(port.addr));
module->addFf(NEW_ID, port.addr, addr_q);
SigSpec data_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#data_q", mem.memid.unescape(), i)), GetSize(port.data));
SigSpec data_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#data_q", memid, i)), GetSize(port.data));
module->addFf(NEW_ID, port.data, data_q);
port.clk = State::S0;
passes/sat/cutpoint.cc
+5 -5
View File
@@ -132,7 +132,7 @@ struct CutpointPass : public Pass {
if (cell->input(conn.first))
for (auto bit : sigmap(conn.second))
if (wire_drivers.count(bit)) {
log_debug(" Treating inout port '%s' as input.\n", conn.first.unescape());
log_debug(" Treating inout port '%s' as input.\n", PooledName(design, conn.first).unescape());
do_cut = false;
break;
}
@@ -140,7 +140,7 @@ struct CutpointPass : public Pass {
if (do_cut) {
module->connect(conn.second, flag_undef ? Const(State::Sx, GetSize(conn.second)) : module->Anyseq(NEW_ID, GetSize(conn.second)));
if (cell->input(conn.first)) {
log_debug(" Treating inout port '%s' as output.\n", conn.first.unescape());
log_debug(" Treating inout port '%s' as output.\n", PooledName(design, conn.first).unescape());
for (auto bit : sigmap(conn.second))
wire_drivers.insert(bit);
}
@@ -149,8 +149,8 @@ struct CutpointPass : public Pass {
}
RTLIL::Cell *scopeinfo = nullptr;
auto cell_name = cell->name;
if (flag_scopeinfo && cell_name.isPublic()) {
IdString cell_name = cell->name;
if (flag_scopeinfo && cell->name.isPublic()) {
auto scopeinfo = module->addCell(NEW_ID, ID($scopeinfo));
scopeinfo->setParam(ID::TYPE, RTLIL::Const("blackbox"));
@@ -159,7 +159,7 @@ struct CutpointPass : public Pass {
if (attr.first == ID::hdlname)
scopeinfo->attributes.insert(attr);
else
scopeinfo->attributes.emplace(stringf("\\cell_%s", attr.first.unescape()), attr.second);
scopeinfo->attributes.emplace(design->twines.add(stringf("\\cell_%s", design->twines.unescaped_str(attr.first))), attr.second);
}
}
passes/sat/eval.cc
+17 -14
View File
@@ -149,7 +149,7 @@ struct VlogHammerReporter
for (auto c : module->cells())
if (!satgen.importCell(c))
log_error("Failed to import cell %s (type %s) to SAT database.\n", c->name.unescape(), c->type.unescape());
log_error("Failed to import cell %s (type %s) to SAT database.\n", c, c->type.unescape());
ez->assume(satgen.signals_eq(recorded_set_vars, recorded_set_vals));
@@ -262,9 +262,9 @@ struct VlogHammerReporter
if (module == modules.front()) {
RTLIL::SigSpec sig(wire);
if (!ce.eval(sig))
log_error("Can't read back value for port %s!\n", inputs[i].unescape());
log_error("Can't read back value for port %s!\n", PooledName(design, inputs[i]).unescape());
input_pattern_list += stringf(" %s", sig.as_const().as_string());
log("++PAT++ %d %s %s #\n", idx, inputs[i].unescape(), sig.as_const().as_string());
log("++PAT++ %d %s %s #\n", idx, PooledName(design, inputs[i]).unescape(), sig.as_const().as_string());
}
}
@@ -305,29 +305,30 @@ struct VlogHammerReporter
VlogHammerReporter(RTLIL::Design *design, std::string module_prefix, std::string module_list, std::string input_list, std::string pattern_list) : design(design)
{
for (auto name : split(module_list, ",")) {
RTLIL::IdString esc_name = RTLIL::escape_id(module_prefix + name);
if (design->module(esc_name) == nullptr)
IdString esc_name = design->twines.add(RTLIL::escape_id(module_prefix + name));
RTLIL::Module *mod = design->module(esc_name);
if (mod == nullptr)
log_error("Can't find module %s in current design!\n", name);
log("Using module %s (%s).\n", esc_name, name);
modules.push_back(design->module(esc_name));
log("Using module %s (%s).\n", design->twines.str(esc_name), name);
modules.push_back(mod);
module_names.push_back(name);
}
total_input_width = 0;
for (auto name : split(input_list, ",")) {
int width = -1;
RTLIL::IdString esc_name = RTLIL::escape_id(name);
IdString esc_name = design->twines.add(RTLIL::escape_id(name));
for (auto mod : modules) {
if (mod->wire(esc_name) == nullptr)
log_error("Can't find input %s in module %s!\n", name, mod->name.unescape());
RTLIL::Wire *port = mod->wire(esc_name);
if (port == nullptr)
log_error("Can't find input %s in module %s!\n", name, mod->name.unescape());
if (!port->port_input || port->port_output)
log_error("Wire %s in module %s is not an input!\n", name, mod->name.unescape());
if (width >= 0 && width != port->width)
log_error("Port %s has different sizes in the different modules!\n", name);
width = port->width;
}
log("Using input port %s with width %d.\n", esc_name, width);
log("Using input port %s with width %d.\n", design->twines.str(esc_name), width);
inputs.push_back(esc_name);
input_widths.push_back(width);
total_input_width += width;
@@ -414,11 +415,13 @@ struct EvalPass : public Pass {
/* this should only be used for regression testing of ConstEval -- see vloghammer */
std::string mod1_name = RTLIL::escape_id(args[++argidx]);
std::string mod2_name = RTLIL::escape_id(args[++argidx]);
if (design->module(mod1_name) == nullptr)
RTLIL::Module *mod1 = design->module(design->twines.find(mod1_name));
RTLIL::Module *mod2 = design->module(design->twines.find(mod2_name));
if (mod1 == nullptr)
log_error("Can't find module `%s'!\n", mod1_name);
if (design->module(mod2_name) == nullptr)
if (mod2 == nullptr)
log_error("Can't find module `%s'!\n", mod2_name);
BruteForceEquivChecker checker(design->module(mod1_name), design->module(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x");
BruteForceEquivChecker checker(mod1, mod2, args[argidx-2] == "-brute_force_equiv_checker_x");
if (checker.errors > 0)
log_cmd_error("Modules are not equivalent!\n");
log("Verified %s = %s (using brute-force check on %d cases).\n",
passes/sat/expose.cc
+14 -8
View File
@@ -41,7 +41,7 @@ struct dff_map_bit_info_t {
bool consider_wire(RTLIL::Wire *wire, std::map<RTLIL::IdString, dff_map_info_t> &dff_dq_map)
{
if (wire->name[0] == '$' || dff_dq_map.count(wire->name))
if (!wire->name.isPublic() || dff_dq_map.count(wire->name))
return false;
if (wire->port_input)
return false;
@@ -50,9 +50,9 @@ bool consider_wire(RTLIL::Wire *wire, std::map<RTLIL::IdString, dff_map_info_t>
bool consider_cell(RTLIL::Design *design, std::set<RTLIL::IdString> &dff_cells, RTLIL::Cell *cell)
{
if (cell->name[0] == '$' || dff_cells.count(cell->name))
if (!cell->name.isPublic() || dff_cells.count(cell->name))
return false;
if (cell->type[0] == '\\' && (design->module(cell->type) == nullptr))
if (cell->type.isPublic() && (design->module(cell->type) == nullptr))
return false;
return true;
}
@@ -210,10 +210,16 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Mo
RTLIL::Wire *add_new_wire(RTLIL::Module *module, RTLIL::IdString name, int width = 1)
{
if (module->count_id(name))
log_error("Attempting to create wire %s, but a wire of this name exists already! Hint: Try another value for -sep.\n", name.unescape());
log_error("Attempting to create wire %s, but a wire of this name exists already! Hint: Try another value for -sep.\n",
module->design->twines.unescaped_str(name));
return module->addWire(name, width);
}
RTLIL::Wire *add_new_wire(RTLIL::Module *module, const std::string &name, int width = 1)
{
return add_new_wire(module, module->design->twines.add(name), width);
}
struct ExposePass : public Pass {
ExposePass() : Pass("expose", "convert internal signals to module ports") { }
bool formatted_help() override {
@@ -472,7 +478,7 @@ struct ExposePass : public Pass {
if (!w->port_input) {
w->port_input = true;
log("New module port: %s/%s\n", module, w);
wire_map[w] = NEW_ID;
wire_map[w] = module->design->twines.add(NEW_ID);
}
}
else
@@ -483,7 +489,7 @@ struct ExposePass : public Pass {
}
if (flag_cut) {
wire_map[w] = w->name.str() + sep + "i";
wire_map[w] = module->design->twines.add(w->name.str() + sep + "i");
}
}
}
@@ -542,7 +548,7 @@ struct ExposePass : public Pass {
dff_map_info_t &info = dq.second;
RTLIL::Wire *wire_dummy_q = add_new_wire(module, NEW_ID, 0);
RTLIL::Wire *wire_dummy_q = add_new_wire(module, module->design->twines.add(NEW_ID), 0);
for (auto &cell_name : info.cells) {
RTLIL::Cell *cell = module->cell(cell_name);
@@ -654,7 +660,7 @@ struct ExposePass : public Pass {
{
for (auto &it : cell->connections())
{
RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + it.first.unescape(), it.second.size());
RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + design->twines.unescaped_str(it.first), it.second.size());
if (ct.cell_input(cell->type, it.first))
w->port_output = true;
if (ct.cell_output(cell->type, it.first))
passes/sat/fmcombine.cc
+14 -14
View File
@@ -44,7 +44,7 @@ struct FmcombineWorker
FmcombineWorker(Design *design, IdString orig_type, const opts_t &opts) :
opts(opts), design(design), original(design->module(orig_type)),
orig_type(orig_type), combined_type(stringf("$fmcombine%s", orig_type))
orig_type(orig_type), combined_type(design->twines.add(stringf("$fmcombine%s", design->twines.str(orig_type).c_str())))
{
}
@@ -53,7 +53,7 @@ struct FmcombineWorker
SigSpec newsig;
for (auto chunk : sig.chunks()) {
if (chunk.wire != nullptr)
chunk.wire = module->wire(chunk.wire->name.str() + suffix);
chunk.wire = module->wire(design->twines.add(std::string{chunk.wire->name.str() + suffix}));
newsig.append(chunk);
}
return newsig;
@@ -87,19 +87,19 @@ struct FmcombineWorker
c->attributes = cell->attributes;
for (auto &conn : cell->connections()) {
c->setPort(conn.first.str() + "_gold", import_sig(conn.second, "_gold"));
c->setPort(conn.first.str() + "_gate", import_sig(conn.second, "_gate"));
c->setPort(design->twines.str(conn.first) + "_gold", import_sig(conn.second, "_gold"));
c->setPort(design->twines.str(conn.first) + "_gate", import_sig(conn.second, "_gate"));
}
}
void generate()
{
if (design->module(combined_type)) {
// log("Combined module %s already exists.\n", combined_type.unescape());
// log("Combined module %s already exists.\n", PooledName(design, combined_type).unescape());
return;
}
log("Generating combined module %s from module %s.\n", combined_type.unescape(), orig_type.unescape());
log("Generating combined module %s from module %s.\n", PooledName(design, combined_type).unescape(), PooledName(design, orig_type).unescape());
module = design->addModule(combined_type);
for (auto wire : original->wires()) {
@@ -326,21 +326,21 @@ struct FmcombinePass : public Pass {
}
else if (argidx+3 == args.size())
{
IdString module_name = RTLIL::escape_id(args[argidx++]);
IdString gold_name = RTLIL::escape_id(args[argidx++]);
IdString gate_name = RTLIL::escape_id(args[argidx++]);
IdString module_name = design->twines.add(RTLIL::escape_id(args[argidx++]));
IdString gold_name = design->twines.add(RTLIL::escape_id(args[argidx++]));
IdString gate_name = design->twines.add(RTLIL::escape_id(args[argidx++]));
module = design->module(module_name);
if (module == nullptr)
log_cmd_error("Module %s not found.\n", module_name.unescape());
log_cmd_error("Module %s not found.\n", PooledName(design, module_name).unescape());
gold_cell = module->cell(gold_name);
if (gold_cell == nullptr)
log_cmd_error("Gold cell %s not found in module %s.\n", gold_name.unescape(), module);
log_cmd_error("Gold cell %s not found in module %s.\n", PooledName(design, gold_name).unescape(), module);
gate_cell = module->cell(gate_name);
if (gate_cell == nullptr)
log_cmd_error("Gate cell %s not found in module %s.\n", gate_name.unescape(), module);
log_cmd_error("Gate cell %s not found in module %s.\n", PooledName(design, gate_name).unescape(), module);
}
else
{
@@ -372,11 +372,11 @@ struct FmcombinePass : public Pass {
log("Combining cells %s and %s in module %s into new cell %s.\n", gold_cell, gate_cell, module, cell);
for (auto &conn : gold_cell->connections())
cell->setPort(conn.first.str() + "_gold", conn.second);
cell->setPort(design->twines.str(conn.first) + "_gold", conn.second);
module->remove(gold_cell);
for (auto &conn : gate_cell->connections())
cell->setPort(conn.first.str() + "_gate", conn.second);
cell->setPort(design->twines.str(conn.first) + "_gate", conn.second);
module->remove(gate_cell);
}
} FmcombinePass;
passes/sat/freduce.cc
+1 -1
View File
@@ -597,7 +597,7 @@ struct FreduceWorker
{
std::string filename = stringf("%s_%s_%05d.il", dump_prefix, module, reduce_counter);
log("%s Writing dump file `%s'.\n", reduce_counter ? " " : "", filename);
Pass::call(design, stringf("dump -outfile %s %s", filename, design->selected_active_module.empty() ? module->name.c_str() : ""));
Pass::call(design, stringf("dump -outfile %s %s", filename, design->selected_active_module == IdString::Null ? module->name.str().c_str() : ""));
}
int run()
passes/sat/mutate.cc
+23 -23
View File
@@ -558,7 +558,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
if (opts.none) {
string str = "mutate";
if (!opts.ctrl_name.empty())
str += stringf(" -ctrl %s %d %d", opts.ctrl_name.unescape(), opts.ctrl_width, ctrl_value++);
str += stringf(" -ctrl %s %d %d", design->twines.unescaped_str(opts.ctrl_name), opts.ctrl_width, ctrl_value++);
str += " -mode none";
if (filename.empty())
log("%s\n", str);
@@ -569,20 +569,20 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
for (auto &entry : database) {
string str = "mutate";
if (!opts.ctrl_name.empty())
str += stringf(" -ctrl %s %d %d", opts.ctrl_name.unescape(), opts.ctrl_width, ctrl_value++);
str += stringf(" -ctrl %s %d %d", design->twines.unescaped_str(opts.ctrl_name), opts.ctrl_width, ctrl_value++);
str += stringf(" -mode %s", entry.mode);
if (!entry.module.empty())
str += stringf(" -module %s", entry.module.unescape());
str += stringf(" -module %s", design->twines.unescaped_str(entry.module));
if (!entry.cell.empty())
str += stringf(" -cell %s", entry.cell.unescape());
str += stringf(" -cell %s", design->twines.unescaped_str(entry.cell));
if (!entry.port.empty())
str += stringf(" -port %s", entry.port.unescape());
str += stringf(" -port %s", design->twines.unescaped_str(entry.port));
if (entry.portbit >= 0)
str += stringf(" -portbit %d", entry.portbit);
if (entry.ctrlbit >= 0)
str += stringf(" -ctrlbit %d", entry.ctrlbit);
if (!entry.wire.empty())
str += stringf(" -wire %s", entry.wire.unescape());
str += stringf(" -wire %s", design->twines.unescaped_str(entry.wire));
if (entry.wirebit >= 0)
str += stringf(" -wirebit %d", entry.wirebit);
for (auto &s : entry.src)
@@ -600,7 +600,7 @@ SigSpec mutate_ctrl_sig(Module *module, IdString name, int width)
if (ctrl_wire == nullptr)
{
log("Adding ctrl port %s to module %s.\n", name.unescape(), module);
log("Adding ctrl port %s to module %s.\n", PooledName(module, name).unescape(), module);
ctrl_wire = module->addWire(name, width);
ctrl_wire->port_input = true;
@@ -652,13 +652,13 @@ void mutate_inv(Design *design, const mutate_opts_t &opts)
if (cell->input(opts.port))
{
log("Add input inverter at %s.%s.%s[%d].\n", module, cell, opts.port.unescape(), opts.portbit);
log("Add input inverter at %s.%s.%s[%d].\n", module, cell, PooledName(design, opts.port).unescape(), opts.portbit);
SigBit outbit = module->Not(NEW_ID, bit);
bit = mutate_ctrl_mux(module, opts, bit, outbit);
}
else
{
log("Add output inverter at %s.%s.%s[%d].\n", module, cell, opts.port.unescape(), opts.portbit);
log("Add output inverter at %s.%s.%s[%d].\n", module, cell, PooledName(design, opts.port).unescape(), opts.portbit);
SigBit inbit = module->addWire(NEW_ID);
SigBit outbit = module->Not(NEW_ID, inbit);
module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
@@ -680,13 +680,13 @@ void mutate_const(Design *design, const mutate_opts_t &opts, bool one)
if (cell->input(opts.port))
{
log("Add input constant %d at %s.%s.%s[%d].\n", one ? 1 : 0, module, cell, opts.port.unescape(), opts.portbit);
log("Add input constant %d at %s.%s.%s[%d].\n", one ? 1 : 0, module, cell, PooledName(design, opts.port).unescape(), opts.portbit);
SigBit outbit = one ? State::S1 : State::S0;
bit = mutate_ctrl_mux(module, opts, bit, outbit);
}
else
{
log("Add output constant %d at %s.%s.%s[%d].\n", one ? 1 : 0, module, cell, opts.port.unescape(), opts.portbit);
log("Add output constant %d at %s.%s.%s[%d].\n", one ? 1 : 0, module, cell, PooledName(design, opts.port).unescape(), opts.portbit);
SigBit inbit = module->addWire(NEW_ID);
SigBit outbit = one ? State::S1 : State::S0;
module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
@@ -709,13 +709,13 @@ void mutate_cnot(Design *design, const mutate_opts_t &opts, bool one)
if (cell->input(opts.port))
{
log("Add input cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, module, cell, opts.port.unescape(), opts.portbit, opts.ctrlbit);
log("Add input cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, module, cell, PooledName(design, opts.port).unescape(), opts.portbit, opts.ctrlbit);
SigBit outbit = one ? module->Xor(NEW_ID, bit, ctrl) : module->Xnor(NEW_ID, bit, ctrl);
bit = mutate_ctrl_mux(module, opts, bit, outbit);
}
else
{
log("Add output cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, module, cell, opts.port.unescape(), opts.portbit, opts.ctrlbit);
log("Add output cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, module, cell, PooledName(design, opts.port).unescape(), opts.portbit, opts.ctrlbit);
SigBit inbit = module->addWire(NEW_ID);
SigBit outbit = one ? module->Xor(NEW_ID, inbit, ctrl) : module->Xnor(NEW_ID, inbit, ctrl);
module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
@@ -835,21 +835,21 @@ struct MutatePass : public Pass {
continue;
}
if (args[argidx] == "-ctrl" && argidx+3 < args.size()) {
opts.ctrl_name = RTLIL::escape_id(args[++argidx]);
opts.ctrl_name = design->twines.add(RTLIL::escape_id(args[++argidx]));
opts.ctrl_width = atoi(args[++argidx].c_str());
opts.ctrl_value = atoi(args[++argidx].c_str());
continue;
}
if (args[argidx] == "-module" && argidx+1 < args.size()) {
opts.module = RTLIL::escape_id(args[++argidx]);
opts.module = design->twines.add(RTLIL::escape_id(args[++argidx]));
continue;
}
if (args[argidx] == "-cell" && argidx+1 < args.size()) {
opts.cell = RTLIL::escape_id(args[++argidx]);
opts.cell = design->twines.add(RTLIL::escape_id(args[++argidx]));
continue;
}
if (args[argidx] == "-port" && argidx+1 < args.size()) {
opts.port = RTLIL::escape_id(args[++argidx]);
opts.port = design->twines.add(RTLIL::escape_id(args[++argidx]));
continue;
}
if (args[argidx] == "-portbit" && argidx+1 < args.size()) {
@@ -861,7 +861,7 @@ struct MutatePass : public Pass {
continue;
}
if (args[argidx] == "-wire" && argidx+1 < args.size()) {
opts.wire = RTLIL::escape_id(args[++argidx]);
opts.wire = design->twines.add(RTLIL::escape_id(args[++argidx]));
continue;
}
if (args[argidx] == "-wirebit" && argidx+1 < args.size()) {
@@ -947,26 +947,26 @@ struct MutatePass : public Pass {
Module *module = design->module(opts.module);
if (module == nullptr)
log_cmd_error("Module %s not found.\n", opts.module.unescape());
log_cmd_error("Module %s not found.\n", PooledName(design, opts.module).unescape());
if (opts.cell.empty())
log_cmd_error("Missing -cell argument.\n");
Cell *cell = module->cell(opts.cell);
if (cell == nullptr)
log_cmd_error("Cell %s not found in module %s.\n", opts.cell.unescape(), opts.module.unescape());
log_cmd_error("Cell %s not found in module %s.\n", PooledName(design, opts.cell).unescape(), PooledName(design, opts.module).unescape());
if (opts.port.empty())
log_cmd_error("Missing -port argument.\n");
if (!cell->hasPort(opts.port))
log_cmd_error("Port %s not found on cell %s.%s.\n", opts.port.unescape(), opts.module.unescape(), opts.cell.unescape());
log_cmd_error("Port %s not found on cell %s.%s.\n", PooledName(design, opts.port).unescape(), PooledName(design, opts.module).unescape(), PooledName(design, opts.cell).unescape());
if (opts.portbit < 0)
log_cmd_error("Missing -portbit argument.\n");
if (GetSize(cell->getPort(opts.port)) <= opts.portbit)
log_cmd_error("Out-of-range -portbit argument for port %s on cell %s.%s.\n", opts.port.unescape(), opts.module.unescape(), opts.cell.unescape());
log_cmd_error("Out-of-range -portbit argument for port %s on cell %s.%s.\n", PooledName(design, opts.port).unescape(), PooledName(design, opts.module).unescape(), PooledName(design, opts.cell).unescape());
if (opts.mode == "inv") {
mutate_inv(design, opts);
@@ -982,7 +982,7 @@ struct MutatePass : public Pass {
log_cmd_error("Missing -ctrlbit argument.\n");
if (GetSize(cell->getPort(opts.port)) <= opts.ctrlbit)
log_cmd_error("Out-of-range -ctrlbit argument for port %s on cell %s.%s.\n", opts.port.unescape(), opts.module.unescape(), opts.cell.unescape());
log_cmd_error("Out-of-range -ctrlbit argument for port %s on cell %s.%s.\n", PooledName(design, opts.port).unescape(), PooledName(design, opts.module).unescape(), PooledName(design, opts.cell).unescape());
if (opts.mode == "cnot0" || opts.mode == "cnot1") {
mutate_cnot(design, opts, opts.mode == "cnot1");
passes/sat/qbfsat.h
+1 -1
View File
@@ -68,7 +68,7 @@ struct QbfSolutionType {
for (auto cell : module->cells()) {
pool<std::string> cell_src = cell->get_strpool_attribute(ID::src);
auto pos = hole_to_value.find(cell_src);
if (pos != hole_to_value.end() && cell->type.in("$anyconst", "$anyseq")) {
if (pos != hole_to_value.end() && cell->type.in(ID($anyconst), ID($anyseq))) {
RTLIL::SigSpec port_y = cell->getPort(ID::Y);
for (int i = GetSize(port_y) - 1; i >= 0; --i) {
hole_loc_idx_to_sigbit[std::make_pair(pos->first, i)] = port_y[i];
passes/sat/recover_names.cc
+8 -8
View File
@@ -42,7 +42,7 @@ PRIVATE_NAMESPACE_BEGIN
// Similar to a SigBit; but module-independent
struct IdBit {
IdBit() : name(), bit(0) {};
IdBit() : name(IdString::Null), bit(0) {};
IdBit(IdString name, int bit = 0) : name(name), bit(bit) {};
bool operator==(const IdBit &other) const { return name == other.name && bit == other.bit; };
@@ -207,7 +207,7 @@ struct RecoverModuleWorker {
void compute_depths(const dict<IdBit, IdBit> &anchor_bits)
{
dict<SigBit, pool<IdString>> bit_drivers, bit_users;
TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
TopoSort<IdString> toposort;
for (auto cell : flat->cells())
for (auto conn : cell->connections())
@@ -380,11 +380,11 @@ struct RecoverModuleWorker {
if (root2buffered.count(gate_bit)) {
int buf_idx = 0;
for (auto buf_bit : root2buffered.at(gate_bit)) {
std::string buf_name_str = stringf("%s_buf_%d", pair.second.bit.name, ++buf_idx);
std::string buf_name_str = stringf("%s_buf_%d", design->twines.str(pair.second.bit.name).c_str(), ++buf_idx);
if (buf_name_str[0] == '\\')
buf_name_str[0] = '$';
rename_map[buf_bit] = std::make_pair(
InvBit(IdBit(IdString(buf_name_str), pair.second.bit.bit), pair.second.inverted), gold_wire);
InvBit(IdBit(design->twines.add(std::string{buf_name_str}), pair.second.bit.bit), pair.second.inverted), gold_wire);
}
}
}
@@ -396,11 +396,11 @@ struct RecoverModuleWorker {
bool must_invert_name = rule.second.first.inverted;
while (must_invert_name ||
(mod->wire(new_name.name) && !unused_bits.count(SigBit(mod->wire(new_name.name), new_name.bit)))) {
std::string new_name_str = stringf("%s_%s_%d", rule.second.first.bit.name,
std::string new_name_str = stringf("%s_%s_%d", design->twines.str(rule.second.first.bit.name).c_str(),
rule.second.first.inverted ? "inv" : "dup", ++dup_idx);
if (new_name_str[0] == '\\')
new_name_str[0] = '$';
new_name.name = IdString(new_name_str);
new_name.name = design->twines.add(std::string{new_name_str});
must_invert_name = false;
}
// Create the wire if needed
@@ -641,8 +641,8 @@ struct RecoverNamesWorker {
for (auto gate_bit : gate_bits) {
if (solved_gate.count(gate_bit.bit))
continue;
log_debug(" attempting to prove %s[%d] == %s%s[%d]\n", gold_bit.name.unescape(), gold_bit.bit,
gate_bit.inverted ? "" : "!", gate_bit.bit.name.unescape(), gate_bit.bit.bit);
log_debug(" attempting to prove %s[%d] == %s%s[%d]\n", PooledName(design, gold_bit.name).unescape(), gold_bit.bit,
gate_bit.inverted ? "" : "!", PooledName(design, gate_bit.bit.name).unescape(), gate_bit.bit.bit);
if (!prove_equiv(gold_worker, gate_worker, gold_anchors, gate_anchors, gold_bit, gate_bit.bit, gate_bit.inverted))
continue;
log_debug(" success!\n");
passes/sat/sat.cc
+2 -2
View File
@@ -706,13 +706,13 @@ struct SatHelper
fprintf(f, "$end\n");
fprintf(f, "$comment\n");
fprintf(f, " Generated from SAT problem in module %s (declared at %s)\n",
module->name.c_str(), module_fname.c_str());
module->name.str().c_str(), module_fname.c_str());
fprintf(f, "$end\n");
// VCD has some limits on internal (non-display) identifier names, so make legal ones
std::map<std::string, std::string> vcdnames;
fprintf(f, "$scope module %s $end\n", module->name.c_str());
fprintf(f, "$scope module %s $end\n", module->name.str().c_str());
for (auto &info : modelInfo)
{
if (vcdnames.find(info.description) != vcdnames.end())
passes/sat/synthprop.cc
+11 -11
View File
@@ -37,8 +37,6 @@ struct SynthPropWorker
// pointer to main design
RTLIL::Design *design;
RTLIL::IdString top_name;
RTLIL::Module *module;
std::string map_file;
@@ -52,7 +50,7 @@ struct SynthPropWorker
bool reset_pol;
// basic contrcutor
SynthPropWorker(RTLIL::Design *design) : design(design), or_outputs(false), port_name(RTLIL::escape_id("assertions")) {}
SynthPropWorker(RTLIL::Design *design) : design(design), or_outputs(false), port_name(design->twines.add(std::string("\\assertions"))) {}
void tracing(RTLIL::Module *mod, int depth, TrackingData &tracing_data, std::string hier_path);
void run();
@@ -95,9 +93,11 @@ void SynthPropWorker::run()
TrackingData tracing_data;
tracing(module, 0, tracing_data, module->name.unescape());
IdString port_ref = port_name;
for (auto &data : tracing_data) {
if (data.second.names.size() == 0) continue;
RTLIL::Wire *wire = data.first->addWire(port_name, data.second.names.size());
RTLIL::Wire *wire = data.first->addWire(port_ref, data.second.names.size());
wire->port_output = true;
data.first->fixup_ports();
}
@@ -105,7 +105,7 @@ void SynthPropWorker::run()
RTLIL::Wire *output = nullptr;
for (auto &data : tracing_data) {
int num = 0;
RTLIL::Wire *port_wire = data.first->wire(port_name);
RTLIL::Wire *port_wire = data.first->wire(port_ref);
if (!reset_name.empty() && data.first == module) {
port_wire = data.first->addWire(NEW_ID, data.second.names.size());
output = port_wire;
@@ -130,10 +130,10 @@ void SynthPropWorker::run()
if (RTLIL::Module *submod = design->module(cell->type)) {
if (tracing_data[submod].names.size() > 0) {
if (!or_outputs) {
cell->setPort(port_name, SigChunk(port_wire, num, tracing_data[submod].names.size()));
cell->setPort(port_ref, SigChunk(port_wire, num, tracing_data[submod].names.size()));
} else {
RTLIL::Wire *result_wire = data.first->addWire(NEW_ID);
cell->setPort(port_name, result_wire);
cell->setPort(port_ref, result_wire);
connected.emplace(result_wire);
}
num += tracing_data[submod].names.size();
@@ -163,7 +163,7 @@ void SynthPropWorker::run()
SigSpec reset = module->wire(reset_name);
reset.extend_u0(width, true);
module->addDlatchsr(NEW_ID, State::S1, Const(State::S0,width), reset, output, module->wire(port_name), true, true, reset_pol);
module->addDlatchsr(NEW_ID, State::S1, Const(State::S0,width), reset, output, module->wire(port_ref), true, true, reset_pol);
}
if (!map_file.empty()) {
@@ -224,7 +224,7 @@ struct SyntProperties : public Pass {
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-name" && argidx+1 < args.size()) {
worker.port_name = RTLIL::escape_id(args[++argidx]);
worker.port_name = design->twines.add(RTLIL::escape_id(args[++argidx]));
continue;
}
if (args[argidx] == "-map" && argidx+1 < args.size()) {
@@ -232,12 +232,12 @@ struct SyntProperties : public Pass {
continue;
}
if (args[argidx] == "-reset" && argidx+1 < args.size()) {
worker.reset_name = RTLIL::escape_id(args[++argidx]);
worker.reset_name = design->twines.add(RTLIL::escape_id(args[++argidx]));
worker.reset_pol = true;
continue;
}
if (args[argidx] == "-resetn" && argidx+1 < args.size()) {
worker.reset_name = RTLIL::escape_id(args[++argidx]);
worker.reset_name = design->twines.add(RTLIL::escape_id(args[++argidx]));
worker.reset_pol = false;
continue;
}
passes/techmap/abc_new.cc
+2 -2
View File
@@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
std::vector<Module*> order_modules(Design *design, std::vector<Module *> modules)
{
std::set<Module *> modules_set(modules.begin(), modules.end());
using Order = IdString::compare_ptr_by_name<RTLIL::NamedObject>;
using Order = IdString::compare_ptr_by_name<RTLIL::Module>;
TopoSort<Module*, Order> sort;
for (auto m : modules) {
@@ -192,7 +192,7 @@ struct AbcNewPass : public ScriptPass {
}
run(stringf(" abc9_ops -write_box %s/input.box", tmpdir));
run(stringf(" write_xaiger2 -mapping_prep -map2 %s/input.map2 %s/input.xaig", tmpdir, tmpdir));
run(stringf(" write_xaiger2 -mapping_prep -map-refs -map2 %s/input.map2 %s/input.xaig", tmpdir, tmpdir));
run(stringf(" abc9_exe %s -cwd %s -box %s/input.box", exe_options, tmpdir, tmpdir));
run(stringf(" read_aiger -xaiger -module_name %s$abc9 %s/output.aig",
modname, tmpdir));
passes/techmap/aigmap.cc
+2 -2
View File
@@ -151,14 +151,14 @@ struct AigmapPass : public Pass {
stat_replaced.sort();
log(" replaced %d cell types:\n", GetSize(stat_replaced));
for (auto &it : stat_replaced)
log("%8d %s\n", it.second, it.first.unescape());
log("%8d %s\n", it.second, PooledName(module, it.first).unescape());
}
if (!stat_not_replaced.empty()) {
stat_not_replaced.sort();
log(" not replaced %d cell types:\n", GetSize(stat_not_replaced));
for (auto &it : stat_not_replaced)
log("%8d %s\n", it.second, it.first.unescape());
log("%8d %s\n", it.second, PooledName(module, it.first).unescape());
}
for (auto cell : replaced_cells)
passes/techmap/attrmvcp.cc
+2 -2
View File
@@ -79,7 +79,7 @@ struct AttrmvcpPass : public Pass {
continue;
}
if (arg == "-attr" && argidx+1 < args.size()) {
attrnames.insert(RTLIL::escape_id(args[++argidx]));
attrnames.insert(design->twines.find(RTLIL::escape_id(args[++argidx])));
continue;
}
break;
@@ -121,7 +121,7 @@ struct AttrmvcpPass : public Pass {
for (auto bit : sigmap(wire))
if (net2cells.count(bit))
for (auto cell : net2cells.at(bit)) {
log("Moving attribute %s=%s from %s.%s to %s.%s.\n", attr.first.unescape(), log_const(attr.second),
log("Moving attribute %s=%s from %s.%s to %s.%s.\n", PooledName(design, attr.first).unescape(), log_const(attr.second),
module, wire, module, cell);
cell->attributes[attr.first] = attr.second;
did_something = true;
passes/techmap/booth.cc
+15 -16
View File
@@ -188,9 +188,8 @@ struct BoothPassWorker {
cor_o = module->AndGate(NEW_ID_SUFFIX(name), pp1_nor_pp0, cori_i);
}
void BuildBitwiseFa(Module *mod, std::string name, const SigSpec &sig_a, const SigSpec &sig_b,
const SigSpec &sig_c, const SigSpec &sig_x, const SigSpec &sig_y,
const std::string &src = "")
void BuildBitwiseFa(Module *mod, IdString name, const SigSpec &sig_a, const SigSpec &sig_b,
const SigSpec &sig_c, const SigSpec &sig_x, const SigSpec &sig_y)
{
// We can't emit a single wide full-adder cell here since
// there would typically be feedback loops involving the cells'
@@ -202,8 +201,8 @@ struct BoothPassWorker {
log_assert(sig_a.size() == sig_y.size());
for (int i = 0; i < sig_a.size(); i++)
mod->addFa(stringf("%s[%d]", name, i), sig_a[i], sig_b[i],
sig_c[i], sig_x[i], sig_y[i], src);
mod->addFa(Twine::Suffix{name, stringf("[%d]", i)}, sig_a[i], sig_b[i],
sig_c[i], sig_x[i], sig_y[i]);
}
void run()
@@ -480,7 +479,7 @@ struct BoothPassWorker {
for (auto pp_row : aligned_pp) {
printf("PP_%d \t", pp_ix);
for (unsigned i = 0; i < pp_row.size(); i++)
printf("[%d] %s ", i, pp_row[i] == nullptr ? " 0 " : pp_row[i]->name.c_str());
printf("[%d] %s ", i, pp_row[i] == nullptr ? " 0 " : pp_row[i]->name.str().c_str());
printf("\n");
pp_ix++;
}
@@ -504,11 +503,11 @@ struct BoothPassWorker {
for (auto pp_wire : get<0>(pp)) {
RTLIL::IdString wire_name = pp_wire->name;
printf(" [%d]:%s ", ix, wire_name.c_str());
printf(" [%d]:%s ", ix, module->design->twines.str(wire_name).c_str());
ix++;
}
printf("\n");
printf("\tSign bit to add in: %s\n", sign_bit->name.c_str());
printf("\tSign bit to add in: %s\n", sign_bit->name.str().c_str());
pp_ix++;
}
@@ -521,30 +520,30 @@ struct BoothPassWorker {
printf("CSA Tree column %d\n", i);
int ix = 0;
for (auto csa_elem : csa_tree) {
printf("\tCell %d %s type %s\n", ix, csa_elem->name.c_str(), csa_elem->type.c_str());
printf("\tCell %d %s type %s\n", ix, csa_elem->name.str().c_str(), csa_elem->type.str().c_str());
if (csa_elem->getPort(ID::A) == State::S0)
printf("\tA set to constant 0\n");
else if (csa_elem->getPort(ID::A) == State::S1)
printf("\tA set to constant 1\n");
else
printf("\tA driven by %s\n", csa_elem->getPort(ID::A).as_wire()->name.c_str());
printf("\tA driven by %s\n", csa_elem->getPort(ID::A).as_wire()->name.str().c_str());
if (csa_elem->getPort(ID::B) == State::S0)
printf("\tB set to constant 0\n");
else if (csa_elem->getPort(ID::B) == State::S1)
printf("\tB set to constant 1\n");
else
printf("\tB driven by %s\n", csa_elem->getPort(ID::B).as_wire()->name.c_str());
printf("\tB driven by %s\n", csa_elem->getPort(ID::B).as_wire()->name.str().c_str());
if (csa_elem->getPort(ID::C) == State::S0)
printf("\tC set to constant 0\n");
else if (csa_elem->getPort(ID::C) == State::S1)
printf("\tC set to constant 1\n");
else
printf("\tC driven by %s\n", csa_elem->getPort(ID::C).as_wire()->name.c_str());
printf("\tC driven by %s\n", csa_elem->getPort(ID::C).as_wire()->name.str().c_str());
printf("Carry out: %s\n", csa_elem->getPort(ID::X).as_wire()->name.c_str());
printf("Sum out: %s\n", csa_elem->getPort(ID::Y).as_wire()->name.c_str());
printf("Carry out: %s\n", csa_elem->getPort(ID::X).as_wire()->name.str().c_str());
printf("Sum out: %s\n", csa_elem->getPort(ID::Y).as_wire()->name.str().c_str());
ix++;
}
@@ -1078,7 +1077,7 @@ struct BoothPassWorker {
// 1st row exception: two localized inverters due to sign extension structure
SigBit d08_inv = module->NotGate(NEW_ID_SUFFIX("bfa_0_exc_inv1"), PPij[(0 * dec_count) + dec_count - 1]);
SigBit d18_inv = module->NotGate(NEW_ID_SUFFIX("bfa_0_exc_inv2"), PPij[(1 * dec_count) + dec_count - 1]);
BuildBitwiseFa(module, NEW_ID_SUFFIX("fa_row_0").str(),
BuildBitwiseFa(module, module->design->twines.add(NEW_ID_SUFFIX("fa_row_0")),
/* A */ {State::S0, d08_inv, PPij[(0 * dec_count) + x_sz], PPij.extract((0 * dec_count) + 2, x_sz - 1)},
/* B */ {State::S1, d18_inv, PPij.extract((1 * dec_count), x_sz)},
/* C */ fa_carry[0].extract(1, x_sz + 2),
@@ -1094,7 +1093,7 @@ struct BoothPassWorker {
SigBit d_inv = module->NotGate(NEW_ID_SUFFIX(stringf("bfa_se_inv_%d_L", fa_row_ix)),
PPij[((fa_row_ix + 1) * dec_count) + dec_count - 1]);
BuildBitwiseFa(module, NEW_ID_SUFFIX(stringf("fa_row_%d", fa_row_ix)).str(),
BuildBitwiseFa(module, module->design->twines.add(NEW_ID_SUFFIX(stringf("fa_row_%d", fa_row_ix))),
/* A */ {State::S0, fa_carry[fa_row_ix - 1][fa_count - 1], fa_sum[fa_row_ix - 1].extract(2, x_sz + 2)},
/* B */ {State::S1, d_inv, PPij.extract((fa_row_ix + 1) * dec_count, x_sz), State::S0, State::S0},
passes/techmap/bufnorm.cc
+2 -2
View File
@@ -392,7 +392,7 @@ struct BufnormPass : public Pass {
if (w->name.isPublic())
log(" directly driven by cell %s port %s: %s\n",
cell, conn.first.unescape(), w);
cell, PooledName(cell->module, conn.first).unescape(), w);
for (auto bit : SigSpec(w))
mapped_bits[sigmap(bit)] = bit;
@@ -502,7 +502,7 @@ struct BufnormPass : public Pass {
if (conn.second != newsig) {
log(" fixing input signal on cell %s port %s: %s\n",
cell, conn.first.unescape(), log_signal(newsig));
cell, PooledName(cell->module, conn.first).unescape(), log_signal(newsig));
cell->setPort(conn.first, newsig);
count_updated_cellports++;
}
passes/techmap/clkbufmap.cc
+17 -10
View File
@@ -122,9 +122,16 @@ struct ClkbufmapPass : public Pass {
// If true, use both ther -buf and -inpad cell for input ports that are clocks.
bool buffer_inputs = true;
Module *inpad_mod = design->module(RTLIL::escape_id(inpad_celltype));
IdString buf_celltype_ref = design->twines.add(std::string{RTLIL::escape_id(buf_celltype)});
IdString buf_portname_ref = design->twines.add(std::string{RTLIL::escape_id(buf_portname)});
IdString buf_portname2_ref = design->twines.add(std::string{RTLIL::escape_id(buf_portname2)});
IdString inpad_celltype_ref = design->twines.add(std::string{RTLIL::escape_id(inpad_celltype)});
IdString inpad_portname_ref = design->twines.add(std::string{RTLIL::escape_id(inpad_portname)});
IdString inpad_portname2_ref = design->twines.add(std::string{RTLIL::escape_id(inpad_portname2)});
Module *inpad_mod = design->module(inpad_celltype_ref);
if (inpad_mod) {
Wire *buf_wire = inpad_mod->wire(RTLIL::escape_id(buf_portname));
Wire *buf_wire = inpad_mod->wire(buf_portname_ref);
if (buf_wire && buf_wire->get_bool_attribute(ID::clkbuf_driver))
buffer_inputs = false;
}
@@ -148,7 +155,7 @@ struct ClkbufmapPass : public Pass {
sink_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
auto it = wire->attributes.find(ID::clkbuf_inv);
if (it != wire->attributes.end()) {
IdString in_name = RTLIL::escape_id(it->second.decode_string());
IdString in_name = design->twines.add(std::string{RTLIL::escape_id(it->second.decode_string())});
for (int i = 0; i < GetSize(wire); i++) {
inv_ports_out[make_pair(module->name, make_pair(wire->name, i))] = make_pair(in_name, i);
inv_ports_in[make_pair(module->name, make_pair(in_name, i))] = make_pair(wire->name, i);
@@ -258,22 +265,22 @@ struct ClkbufmapPass : public Pass {
bool is_input = wire->port_input && !inpad_celltype.empty() && module->get_bool_attribute(ID::top);
if (!buf_celltype.empty() && (!is_input || buffer_inputs)) {
log("Inserting %s on %s.%s[%d].\n", buf_celltype, module, wire, i);
cell = module->addCell(NEW_ID, RTLIL::escape_id(buf_celltype));
cell = module->addCell(NEW_ID, buf_celltype_ref);
iwire = module->addWire(NEW_ID);
cell->setPort(RTLIL::escape_id(buf_portname), mapped_wire_bit);
cell->setPort(RTLIL::escape_id(buf_portname2), iwire);
cell->setPort(buf_portname_ref, mapped_wire_bit);
cell->setPort(buf_portname2_ref, iwire);
}
if (is_input) {
log("Inserting %s on %s.%s[%d].\n", inpad_celltype, module, wire, i);
RTLIL::Cell *cell2 = module->addCell(NEW_ID, RTLIL::escape_id(inpad_celltype));
RTLIL::Cell *cell2 = module->addCell(NEW_ID, inpad_celltype_ref);
if (iwire) {
cell2->setPort(RTLIL::escape_id(inpad_portname), iwire);
cell2->setPort(inpad_portname_ref, iwire);
} else {
cell2->setPort(RTLIL::escape_id(inpad_portname), mapped_wire_bit);
cell2->setPort(inpad_portname_ref, mapped_wire_bit);
cell = cell2;
}
iwire = module->addWire(NEW_ID);
cell2->setPort(RTLIL::escape_id(inpad_portname2), iwire);
cell2->setPort(inpad_portname2_ref, iwire);
}
if (iwire)
buffered_bits[mapped_wire_bit] = make_pair(cell, iwire);
passes/techmap/clockgate.cc
+7 -6
View File
@@ -8,11 +8,11 @@ USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct ClockGateCell {
IdString name;
IdString ce_pin;
IdString clk_in_pin;
IdString clk_out_pin;
std::vector<IdString> tie_lo_pins;
std::string name;
std::string ce_pin;
std::string clk_in_pin;
std::string clk_out_pin;
std::vector<std::string> tie_lo_pins;
};
ClockGateCell icg_from_arg(std::string& name, std::string& str) {
@@ -371,7 +371,8 @@ struct ClockgatePass : public Pass {
if (!matching_icg_desc)
continue;
Cell* icg = module->addCell(NEW_ID, matching_icg_desc->name);
auto& twines = module->design->twines;
Cell* icg = module->addCell(NEW_ID, twines.add(std::string{matching_icg_desc->name}));
icg->setPort(matching_icg_desc->ce_pin, clk.ce_bit);
icg->setPort(matching_icg_desc->clk_in_pin, clk.clk_bit);
gclk.new_net = module->addWire(NEW_ID);
passes/techmap/constmap.cc
+12 -7
View File
@@ -25,6 +25,7 @@ USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
static std::string celltype, cell_portname, cell_paramname;
static IdString celltype_ref, cell_portname_ref, cell_paramname_ref;
static RTLIL::Module *module;
static RTLIL::SigChunk value;
@@ -33,9 +34,9 @@ void constmap_worker(RTLIL::SigSpec &sig)
{
if (sig.is_fully_const()){
value = module->addWire(NEW_ID, sig.size());
RTLIL::Cell *cell = module->addCell(NEW_ID, celltype);
cell->setParam(cell_paramname, sig.as_const());
cell->setPort(cell_portname, value);
RTLIL::Cell *cell = module->addCell(NEW_ID, celltype_ref);
cell->setParam(cell_paramname_ref, sig.as_const());
cell->setPort(cell_portname_ref, value);
sig = value;
}
}
@@ -74,11 +75,15 @@ struct ConstmapPass : public Pass {
if (celltype.empty())
log_cmd_error("Missing required option -cell.\n");
if (design->has(celltype)) {
Module *existing = design->module(celltype);
celltype_ref = design->twines.add(std::string{celltype});
cell_portname_ref = design->twines.add(std::string{cell_portname});
cell_paramname_ref = design->twines.add(std::string{cell_paramname});
if (design->has(celltype_ref)) {
Module *existing = design->module(celltype_ref);
bool has_port = false;
for (auto &p : existing->ports){
if (p == cell_portname){
if (p == cell_portname_ref){
has_port = true;
break;
}
@@ -88,7 +93,7 @@ struct ConstmapPass : public Pass {
bool has_param = false;
for (auto &p : existing->avail_parameters){
if (p == cell_paramname)
if (p == cell_paramname_ref)
has_param = true;
}
passes/techmap/dffinit.cc
+8 -7
View File
@@ -78,9 +78,10 @@ struct DffinitPass : public Pass {
continue;
}
if (args[argidx] == "-ff" && argidx+3 < args.size()) {
IdString cell_name = RTLIL::escape_id(args[++argidx]);
IdString output_port = RTLIL::escape_id(args[++argidx]);
IdString init_param = RTLIL::escape_id(args[++argidx]);
TwineSearch search(&design->twines);
IdString cell_name = search.find(RTLIL::escape_id(args[++argidx]));
IdString output_port = search.find(RTLIL::escape_id(args[++argidx]));
IdString init_param = search.find(RTLIL::escape_id(args[++argidx]));
ff_types[cell_name][output_port] = init_param;
continue;
}
@@ -123,14 +124,14 @@ struct DffinitPass : public Pass {
if (noreinit && value[i] != State::Sx && value[i] != initval[i])
log_error("Trying to assign a different init value for %s.%s.%s which technically "
"have a conflicted init value.\n",
module, cell, it.second.unescape());
module, cell, PooledName(design, it.second).unescape());
value.set(i, initval[i]);
}
if (highlow_mode && GetSize(value) != 0) {
if (GetSize(value) != 1)
log_error("Multi-bit init value for %s.%s.%s is incompatible with -highlow mode.\n",
module, cell, it.second.unescape());
module, cell, PooledName(design, it.second).unescape());
if (value[0] == State::S1)
value = Const(high_string);
else
@@ -138,8 +139,8 @@ struct DffinitPass : public Pass {
}
if (value.size() != 0) {
log("Setting %s.%s.%s (port=%s, net=%s) to %s.\n", module, cell, it.second.unescape(),
it.first.unescape(), log_signal(sig), log_signal(value));
log("Setting %s.%s.%s (port=%s, net=%s) to %s.\n", module, cell, PooledName(design, it.second).unescape(),
PooledName(design, it.first).unescape(), log_signal(sig), log_signal(value));
cell->setParam(it.second, value);
}
}
passes/techmap/extract_counter.cc
+3 -3
View File
@@ -697,7 +697,7 @@ void counter_worker(
//Hook up any parallel outputs
for(auto load : extract.pouts)
{
log(" Counter has parallel output to cell %s port %s\n", load.cell->name.unescape(), load.port.unescape());
log(" Counter has parallel output to cell %s port %s\n", cell->name.unescape(), PooledName(load.cell->module, load.port).unescape());
}
if(extract.has_pout)
{
@@ -817,13 +817,13 @@ struct ExtractCounterPass : public Pass {
{
if(pouts[i] == ',')
{
settings.parallel_cells.insert(RTLIL::escape_id(tmp));
settings.parallel_cells.insert(design->twines.add(RTLIL::escape_id(tmp)));
tmp = "";
}
else
tmp += pouts[i];
}
settings.parallel_cells.insert(RTLIL::escape_id(tmp));
settings.parallel_cells.insert(design->twines.add(RTLIL::escape_id(tmp)));
continue;
}
passes/techmap/extractinv.cc
+10 -6
View File
@@ -80,6 +80,10 @@ struct ExtractinvPass : public Pass {
if (inv_celltype.empty())
log_error("The -inv option is required.\n");
IdString inv_celltype_ref = design->twines.add(RTLIL::escape_id(inv_celltype));
IdString inv_portname_ref = design->twines.add(RTLIL::escape_id(inv_portname));
IdString inv_portname2_ref = design->twines.add(RTLIL::escape_id(inv_portname2));
for (auto module : design->selected_modules())
{
for (auto cell : module->selected_cells())
@@ -93,14 +97,14 @@ struct ExtractinvPass : public Pass {
auto it = cell_wire->attributes.find(ID::invertible_pin);
if (it == cell_wire->attributes.end())
continue;
IdString param_name = RTLIL::escape_id(it->second.decode_string());
IdString param_name = design->twines.find(RTLIL::escape_id(it->second.decode_string()));
auto it2 = cell->parameters.find(param_name);
// Inversion not used -- skip.
if (it2 == cell->parameters.end())
continue;
SigSpec sig = port.second;
if (it2->second.size() != sig.size())
log_error("The inversion parameter needs to be the same width as the port (%s.%s port %s parameter %s)", module->name.unescape(), cell->type.unescape(), port.first.unescape(), param_name.unescape());
log_error("The inversion parameter needs to be the same width as the port (%s.%s port %s parameter %s)", module->name.unescape(), cell->type.unescape(), PooledName(design, port.first).unescape(), PooledName(design, param_name).unescape());
RTLIL::Const invmask = it2->second;
cell->parameters.erase(param_name);
if (invmask.is_fully_zero())
@@ -108,10 +112,10 @@ struct ExtractinvPass : public Pass {
Wire *iwire = module->addWire(NEW_ID, sig.size());
for (int i = 0; i < sig.size(); i++)
if (invmask[i] == State::S1) {
RTLIL::Cell *icell = module->addCell(NEW_ID, RTLIL::escape_id(inv_celltype));
icell->setPort(RTLIL::escape_id(inv_portname), SigSpec(iwire, i));
icell->setPort(RTLIL::escape_id(inv_portname2), sig[i]);
log("Inserting %s on %s.%s.%s[%d].\n", inv_celltype, module, cell->type.unescape(), port.first.unescape(), i);
RTLIL::Cell *icell = module->addCell(NEW_ID, inv_celltype_ref);
icell->setPort(inv_portname_ref, SigSpec(iwire, i));
icell->setPort(inv_portname2_ref, sig[i]);
log("Inserting %s on %s.%s.%s[%d].\n", inv_celltype, module, cell->type.unescape(), PooledName(design, port.first).unescape(), i);
sig[i] = SigBit(iwire, i);
}
cell->setPort(port.first, sig);
passes/techmap/insbuf.cc
+4 -4
View File
@@ -52,9 +52,9 @@ struct InsbufPass : public Pass {
{
std::string arg = args[argidx];
if (arg == "-buf" && argidx+3 < args.size()) {
celltype = RTLIL::escape_id(args[++argidx]);
in_portname = RTLIL::escape_id(args[++argidx]);
out_portname = RTLIL::escape_id(args[++argidx]);
celltype = design->twines.add(std::string{RTLIL::escape_id(args[++argidx])});
in_portname = design->twines.add(std::string{RTLIL::escape_id(args[++argidx])});
out_portname = design->twines.add(std::string{RTLIL::escape_id(args[++argidx])});
continue;
}
if (arg == "-chain") {
@@ -116,7 +116,7 @@ struct InsbufPass : public Pass {
if (s == port.second)
continue;
log("Rewrite %s/%s/%s: %s -> %s\n", module, cell,
port.first.unescape(), log_signal(port.second), log_signal(s));
PooledName(module, port.first).unescape(), log_signal(port.second), log_signal(s));
cell->setPort(port.first, s);
}
}
passes/techmap/iopadmap.cc
+18 -18
View File
@@ -164,7 +164,7 @@ struct IopadmapPass : public Pass {
std::string ignore_portname2;
while (!ignore_portname.empty()) {
split_portname_pair(ignore_portname, ignore_portname2);
ignore.insert(make_pair(RTLIL::escape_id(ignore_celltype), RTLIL::escape_id(ignore_portname)));
ignore.insert(make_pair(design->twines.add(RTLIL::escape_id(ignore_celltype)), design->twines.add(RTLIL::escape_id(ignore_portname))));
ignore_portname = ignore_portname2;
}
@@ -187,15 +187,15 @@ struct IopadmapPass : public Pass {
extra_args(args, argidx, design);
if (!inpad_portname_pad.empty())
ignore.insert(make_pair(RTLIL::escape_id(inpad_celltype), RTLIL::escape_id(inpad_portname_pad)));
ignore.insert(make_pair(design->twines.add(RTLIL::escape_id(inpad_celltype)), design->twines.add(RTLIL::escape_id(inpad_portname_pad))));
if (!outpad_portname_pad.empty())
ignore.insert(make_pair(RTLIL::escape_id(outpad_celltype), RTLIL::escape_id(outpad_portname_pad)));
ignore.insert(make_pair(design->twines.add(RTLIL::escape_id(outpad_celltype)), design->twines.add(RTLIL::escape_id(outpad_portname_pad))));
if (!inoutpad_portname_pad.empty())
ignore.insert(make_pair(RTLIL::escape_id(inoutpad_celltype), RTLIL::escape_id(inoutpad_portname_pad)));
ignore.insert(make_pair(design->twines.add(RTLIL::escape_id(inoutpad_celltype)), design->twines.add(RTLIL::escape_id(inoutpad_portname_pad))));
if (!toutpad_portname_pad.empty())
ignore.insert(make_pair(RTLIL::escape_id(toutpad_celltype), RTLIL::escape_id(toutpad_portname_pad)));
ignore.insert(make_pair(design->twines.add(RTLIL::escape_id(toutpad_celltype)), design->twines.add(RTLIL::escape_id(toutpad_portname_pad))));
if (!tinoutpad_portname_pad.empty())
ignore.insert(make_pair(RTLIL::escape_id(tinoutpad_celltype), RTLIL::escape_id(tinoutpad_portname_pad)));
ignore.insert(make_pair(design->twines.add(RTLIL::escape_id(tinoutpad_celltype)), design->twines.add(RTLIL::escape_id(tinoutpad_portname_pad))));
// Recursively collect list of (module, port, bit) triples that already have buffers.
@@ -214,7 +214,7 @@ struct IopadmapPass : public Pass {
// Collect explicitly-marked already-buffered SigBits.
for (auto wire : module->wires())
if (wire->get_bool_attribute(ID::iopad_external_pin) || ignore.count(make_pair(module->name, wire->name)))
if (wire->get_bool_attribute(ID::iopad_external_pin) || ignore.count(make_pair(IdString(module->name), IdString(wire->name))))
for (int i = 0; i < GetSize(wire); i++)
buf_bits.insert(sigmap(SigBit(wire, i)));
@@ -328,7 +328,7 @@ struct IopadmapPass : public Pass {
Cell *cell = module->addCell(
module->uniquify(stringf("$iopadmap$%s.%s[%d]", module, wire, i)),
RTLIL::escape_id(tinoutpad_celltype));
module->design->twines.add(std::string{RTLIL::escape_id(tinoutpad_celltype)}));
if (tinoutpad_neg_oe)
en_sig = module->NotGate(NEW_ID, en_sig);
@@ -346,13 +346,13 @@ struct IopadmapPass : public Pass {
cell->setPort(RTLIL::escape_id(tinoutpad_portname_i), data_sig);
}
if (!tinoutpad_portname_pad.empty())
rewrite_bits[wire][i] = make_pair(cell, RTLIL::escape_id(tinoutpad_portname_pad));
rewrite_bits[wire][i] = make_pair(cell, module->design->twines.add(std::string{RTLIL::escape_id(tinoutpad_portname_pad)}));
} else {
log("Mapping port %s.%s[%d] using %s.\n", module, wire, i, toutpad_celltype);
Cell *cell = module->addCell(
module->uniquify(stringf("$iopadmap$%s.%s[%d]", module, wire, i)),
RTLIL::escape_id(toutpad_celltype));
module->design->twines.add(std::string{RTLIL::escape_id(toutpad_celltype)}));
if (toutpad_neg_oe)
en_sig = module->NotGate(NEW_ID, en_sig);
@@ -365,7 +365,7 @@ struct IopadmapPass : public Pass {
module->connect(wire_bit, data_sig);
}
if (!toutpad_portname_pad.empty())
rewrite_bits[wire][i] = make_pair(cell, RTLIL::escape_id(toutpad_portname_pad));
rewrite_bits[wire][i] = make_pair(cell, module->design->twines.add(std::string{RTLIL::escape_id(toutpad_portname_pad)}));
}
buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
}
@@ -434,15 +434,15 @@ struct IopadmapPass : public Pass {
RTLIL::Cell *cell = module->addCell(
module->uniquify(stringf("$iopadmap$%s.%s", module->name.unescape(), wire->name.unescape())),
RTLIL::escape_id(celltype));
module->design->twines.add(std::string{RTLIL::escape_id(celltype)}));
cell->setPort(RTLIL::escape_id(portname_int), wire_bit);
if (!portname_pad.empty())
rewrite_bits[wire][i] = make_pair(cell, RTLIL::escape_id(portname_pad));
rewrite_bits[wire][i] = make_pair(cell, module->design->twines.add(std::string{RTLIL::escape_id(portname_pad)}));
if (!widthparam.empty())
cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
cell->parameters[module->design->twines.add(RTLIL::escape_id(widthparam))] = RTLIL::Const(1);
if (!nameparam.empty())
cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(stringf("%s[%d]", wire, i));
cell->parameters[module->design->twines.add(RTLIL::escape_id(nameparam))] = RTLIL::Const(stringf("%s[%d]", wire, i));
cell->attributes[ID::keep] = RTLIL::Const(1);
}
}
@@ -450,7 +450,7 @@ struct IopadmapPass : public Pass {
{
RTLIL::Cell *cell = module->addCell(
module->uniquify(stringf("$iopadmap$%s.%s", module->name.unescape(), wire->name.unescape())),
RTLIL::escape_id(celltype));
module->design->twines.add(std::string{RTLIL::escape_id(celltype)}));
cell->setPort(RTLIL::escape_id(portname_int), RTLIL::SigSpec(wire));
if (!portname_pad.empty()) {
@@ -463,9 +463,9 @@ struct IopadmapPass : public Pass {
cell->setPort(RTLIL::escape_id(portname_pad), RTLIL::SigSpec(new_wire));
}
if (!widthparam.empty())
cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
cell->parameters[module->design->twines.add(RTLIL::escape_id(widthparam))] = RTLIL::Const(wire->width);
if (!nameparam.empty())
cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(wire->name.unescape());
cell->parameters[module->design->twines.add(RTLIL::escape_id(nameparam))] = RTLIL::Const(wire->name.unescape());
cell->attributes[ID::keep] = RTLIL::Const(1);
}
passes/techmap/lut2mux.cc
+1 -1
View File
@@ -97,7 +97,7 @@ struct Lut2muxPass : public Pass {
if (cell->type == ID($lut)) {
IdString cell_name = cell->name;
int count = lut2mux(cell, word_mode);
log("Converted %s.%s to %d MUX cells.\n", module, cell_name.unescape(), count);
log("Converted %s.%s to %d MUX cells.\n", module, PooledName(module, cell_name).unescape(), count);
}
}
}
passes/techmap/muxcover.cc
+2 -1
View File
@@ -170,7 +170,8 @@ struct MuxcoverWorker
return true;
}
char port_name[3] = {'\\', *path, 0};
return follow_muxtree(ret_bit, tree, sigmap(tree.muxes.at(bit)->getPort(port_name)), path+1, false);
Cell *cell = tree.muxes.at(bit);
return follow_muxtree(ret_bit, tree, sigmap(cell->getPort(cell->module->design->twines.add(std::string(port_name)))), path+1, false);
} else {
ret_bit = bit;
return true;
passes/techmap/shregmap.cc
+10 -10
View File
@@ -332,7 +332,7 @@ struct ShregmapWorker
if (opts.ffe) first_cell->setParam(ID(ENPOL), param_enpol);
}
first_cell->type = shreg_cell_type_str;
first_cell->type = first_cell->module->design->twines.add(shreg_cell_type_str);
first_cell->setPort(q_port, last_cell->getPort(q_port));
first_cell->setParam(ID::DEPTH, depth);
@@ -456,9 +456,9 @@ struct ShregmapPass : public Pass {
match_args.push_back("D");
if (GetSize(match_args) < 3)
match_args.push_back("Q");
IdString id_cell_type(RTLIL::escape_id(match_args[0]));
IdString id_d_port_name(RTLIL::escape_id(match_args[1]));
IdString id_q_port_name(RTLIL::escape_id(match_args[2]));
IdString id_cell_type = design->twines.add(std::string{RTLIL::escape_id(match_args[0])});
IdString id_d_port_name = design->twines.add(std::string{RTLIL::escape_id(match_args[1])});
IdString id_q_port_name = design->twines.add(std::string{RTLIL::escape_id(match_args[2])});
opts.ffcells[id_cell_type] = make_pair(id_d_port_name, id_q_port_name);
continue;
}
@@ -519,19 +519,19 @@ struct ShregmapPass : public Pass {
bool en_neg = enpol == "neg" || enpol == "any" || enpol == "any_or_none";
if (clk_pos && en_none)
opts.ffcells[ID($_DFF_P_)] = make_pair(IdString(ID::D), IdString(ID::Q));
opts.ffcells[ID($_DFF_P_)] = make_pair(ID::D, ID::Q);
if (clk_neg && en_none)
opts.ffcells[ID($_DFF_N_)] = make_pair(IdString(ID::D), IdString(ID::Q));
opts.ffcells[ID($_DFF_N_)] = make_pair(ID::D, ID::Q);
if (clk_pos && en_pos)
opts.ffcells[ID($_DFFE_PP_)] = make_pair(IdString(ID::D), IdString(ID::Q));
opts.ffcells[ID($_DFFE_PP_)] = make_pair(ID::D, ID::Q);
if (clk_pos && en_neg)
opts.ffcells[ID($_DFFE_PN_)] = make_pair(IdString(ID::D), IdString(ID::Q));
opts.ffcells[ID($_DFFE_PN_)] = make_pair(ID::D, ID::Q);
if (clk_neg && en_pos)
opts.ffcells[ID($_DFFE_NP_)] = make_pair(IdString(ID::D), IdString(ID::Q));
opts.ffcells[ID($_DFFE_NP_)] = make_pair(ID::D, ID::Q);
if (clk_neg && en_neg)
opts.ffcells[ID($_DFFE_NN_)] = make_pair(IdString(ID::D), IdString(ID::Q));
opts.ffcells[ID($_DFFE_NN_)] = make_pair(ID::D, ID::Q);
if (en_pos || en_neg)
opts.ffe = true;
passes/tests/raise_error.cc
+2 -1
View File
@@ -1,3 +1,4 @@
#include "kernel/rtlil.h"
#include "kernel/yosys.h"
USING_YOSYS_NAMESPACE
@@ -71,7 +72,7 @@ struct RaiseErrorPass : public Pass {
int err_no = 1;
string err_msg = "";
if (err_obj != nullptr) {
log("Raising error from '%s'.\n", err_obj);
log("Raising error from '%s'.\n", design->obj_name(err_obj).c_str());
err_no = err_obj->attributes[ID::raise_error].as_int();
if (err_no > 256) {
err_msg = err_obj->get_string_attribute(ID::raise_error);
passes/tests/test_kogge_stone.cc
+4 -4
View File
@@ -64,8 +64,8 @@ struct TestKoggeStonePass : public Pass {
void execute(std::vector<std::string> args, Design *design) override
{
int width = 16;
IdString gold_name = ID(gold);
IdString gate_name = ID(gate);
IdString gold_name = ID::gold;
IdString gate_name = ID::gate;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
@@ -74,11 +74,11 @@ struct TestKoggeStonePass : public Pass {
continue;
}
if (args[argidx] == "-gold" && argidx + 1 < args.size()) {
gold_name = RTLIL::escape_id(args[++argidx]);
gold_name = design->twines.add(RTLIL::escape_id(args[++argidx]));
continue;
}
if (args[argidx] == "-gate" && argidx + 1 < args.size()) {
gate_name = RTLIL::escape_id(args[++argidx]);
gate_name = design->twines.add(RTLIL::escape_id(args[++argidx]));
continue;
}
break;