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synth_lattice: remove classic ABC mapping

This commit is contained in:
Lofty 2026-08-10 13:52:36 +01:00
parent dd4b6689e8
commit ee75cd3ea0
6 changed files with 27 additions and 75 deletions
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79
techlibs/lattice/synth_lattice.cc
View File

@ -104,10 +104,7 @@ struct SynthLatticePass : public ScriptPass
log(" do not flatten design before synthesis\n"); log(" do not flatten design before synthesis\n");
log("\n"); log("\n");
log(" -dff\n"); log(" -dff\n");
log(" run 'abc'/'abc9' with -dff option\n"); log(" run 'abc9' with -dff option\n");
log("\n");
log(" -retime\n");
log(" run 'abc' with '-dff -D 1' options\n");
log("\n"); log("\n");
log(" -noccu2\n"); log(" -noccu2\n");
log(" do not use CCU2 cells in output netlist\n"); log(" do not use CCU2 cells in output netlist\n");
@ -131,12 +128,6 @@ struct SynthLatticePass : public ScriptPass
log(" -asyncprld\n"); log(" -asyncprld\n");
log(" use async PRLD mode to implement ALDFF (EXPERIMENTAL)\n"); log(" use async PRLD mode to implement ALDFF (EXPERIMENTAL)\n");
log("\n"); log("\n");
log(" -abc2\n");
log(" run two passes of 'abc' for slightly improved logic density\n");
log("\n");
log(" -noabc9\n");
log(" disable use of new ABC9 flow\n");
log("\n");
log(" -iopad\n"); log(" -iopad\n");
log(" insert IO buffers\n"); log(" insert IO buffers\n");
log(" (by default enabled on Nexus FPGAs)\n"); log(" (by default enabled on Nexus FPGAs)\n");
@ -170,9 +161,9 @@ struct SynthLatticePass : public ScriptPass
} }
string top_opt, edif_file, json_file, family, latches; string top_opt, edif_file, json_file, family, latches;
bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, iopad, nodsp, no_rw_check, have_dsp; bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, iopad, nodsp, no_rw_check, have_dsp;
bool cmp2softlogic; bool cmp2softlogic;
string postfix, arith_map, brams_map, dsp_map, cells_map, map_ram_default, widelut_abc; string postfix, arith_map, brams_map, dsp_map, cells_map, map_ram_default;
bool is_nexus; bool is_nexus;
std::vector<DSPRule> dsp_rules; std::vector<DSPRule> dsp_rules;
@ -190,9 +181,6 @@ struct SynthLatticePass : public ScriptPass
asyncprld = false; asyncprld = false;
flatten = true; flatten = true;
dff = false; dff = false;
retime = false;
abc2 = false;
abc9 = true;
iopad = false; iopad = false;
nodsp = false; nodsp = false;
no_rw_check = false; no_rw_check = false;
@ -206,13 +194,11 @@ struct SynthLatticePass : public ScriptPass
is_nexus = false; is_nexus = false;
map_ram_default = ""; map_ram_default = "";
cells_map = ""; cells_map = "";
widelut_abc = "4:7";
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) override void execute(std::vector<std::string> args, RTLIL::Design *design) override
{ {
string run_from, run_to; string run_from, run_to;
bool force_abc9 = false;
bool force_widelut = false; bool force_widelut = false;
bool force_iopad = false; bool force_iopad = false;
clear_flags(); clear_flags();
@ -257,7 +243,7 @@ struct SynthLatticePass : public ScriptPass
continue; continue;
} }
if (args[argidx] == "-retime") { if (args[argidx] == "-retime") {
retime = true; // Removed: ABC9 does not support retiming.
continue; continue;
} }
if (args[argidx] == "-noccu2") { if (args[argidx] == "-noccu2") {
@ -291,17 +277,15 @@ struct SynthLatticePass : public ScriptPass
continue; continue;
} }
if (args[argidx] == "-abc2") { if (args[argidx] == "-abc2") {
abc2 = true; // Removed
continue; continue;
} }
if (args[argidx] == "-abc9") { if (args[argidx] == "-abc9") {
// removed, ABC9 is on by default. // Removed: ABC9 is on by default.
force_abc9 = true;
continue; continue;
} }
if (args[argidx] == "-noabc9") { if (args[argidx] == "-noabc9") {
force_abc9 = true; // Removed: ABC9 is on by default.
abc9 = false;
continue; continue;
} }
if (args[argidx] == "-iopad") { if (args[argidx] == "-iopad") {
@ -358,7 +342,6 @@ struct SynthLatticePass : public ScriptPass
cells_map = "_trellis"; cells_map = "_trellis";
have_dsp = false; have_dsp = false;
if (!force_widelut) nowidelut = true; if (!force_widelut) nowidelut = true;
if (!force_abc9) abc9 = false;
} else if (family == "lifcl" || } else if (family == "lifcl" ||
family == "lfd2nx") { family == "lfd2nx") {
is_nexus = true; is_nexus = true;
@ -370,9 +353,7 @@ struct SynthLatticePass : public ScriptPass
have_dsp = true; have_dsp = true;
map_ram_default = " -no-auto-huge"; map_ram_default = " -no-auto-huge";
cells_map = "_nexus"; cells_map = "_nexus";
widelut_abc = "4:5";
if (!force_iopad) iopad = true; if (!force_iopad) iopad = true;
if (!force_abc9) abc9 = false;
/* } else if (family == "xo" || /* } else if (family == "xo" ||
family == "pm") { family == "pm") {
} else if (family == "xp" || } else if (family == "xp" ||
@ -389,9 +370,6 @@ struct SynthLatticePass : public ScriptPass
if (!design->full_selection()) if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n"); log_cmd_error("This command only operates on fully selected designs!\n");
if (abc9 && retime)
log_cmd_error("-retime option not currently compatible with -abc9!\n");
log_header(design, "Executing SYNTH_LATTICE pass.\n"); log_header(design, "Executing SYNTH_LATTICE pass.\n");
log_push(); log_push();
@ -500,8 +478,6 @@ struct SynthLatticePass : public ScriptPass
run("attrmvcp -attr src -attr LOC -driven t:IB %x:+[I]"); run("attrmvcp -attr src -attr LOC -driven t:IB %x:+[I]");
} }
run("opt -fast"); run("opt -fast");
if (retime || help_mode)
run("abc -dff -D 1", "(only if -retime)");
} }
if (check_label("map_ffs")) if (check_label("map_ffs"))
@ -532,8 +508,8 @@ struct SynthLatticePass : public ScriptPass
run("dfflegalize" + dfflegalize_args, "($_*DFFE_* only if not -nodffe)"); run("dfflegalize" + dfflegalize_args, "($_*DFFE_* only if not -nodffe)");
} }
run("opt_merge"); run("opt_merge");
if ((abc9 && dff) || help_mode) if (dff || help_mode)
run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$_SDFF*", "(only if -abc9 and -dff)"); run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$_SDFF*", "(only if -dff)");
run("techmap -D NO_LUT -map +/lattice/cells_map" + cells_map + ".v"); run("techmap -D NO_LUT -map +/lattice/cells_map" + cells_map + ".v");
run("opt_expr -undriven -mux_undef"); run("opt_expr -undriven -mux_undef");
run("simplemap"); run("simplemap");
@ -544,38 +520,23 @@ struct SynthLatticePass : public ScriptPass
if (check_label("map_luts")) if (check_label("map_luts"))
{ {
if (abc2 || help_mode)
run("abc", " (only if -abc2)");
if (!asyncprld || help_mode) { if (!asyncprld || help_mode) {
if (latches == "error" || help_mode) if (latches == "error" || help_mode)
run("check -latchonly -assert", "(skip if -asyncprld; only if -latches error, the default)"); run("check -latchonly -assert", "(skip if -asyncprld; only if -latches error, the default)");
run("techmap -map +/lattice/latches_map.v", "(skip if -asyncprld)"); run("techmap -map +/lattice/latches_map.v", "(skip if -asyncprld)");
} }
if (abc9) { std::string abc9_opts;
std::string abc9_opts; std::string k = "synth_lattice.abc9.W";
if (nowidelut) if (active_design && active_design->scratchpad.count(k))
abc9_opts += " -maxlut 4"; abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k));
std::string k = "synth_lattice.abc9.W"; else
if (active_design && active_design->scratchpad.count(k)) abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k));
abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k)); if (nowidelut)
else abc9_opts += " -maxlut 4";
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k)); if (dff)
if (nowidelut) abc9_opts += " -dff";
abc9_opts += " -maxlut 4"; run("abc9" + abc9_opts);
if (dff)
abc9_opts += " -dff";
run("abc9" + abc9_opts);
} else {
std::string abc_args = " -dress";
if (nowidelut)
abc_args += " -lut 4";
else
abc_args += " -lut " + widelut_abc;
if (dff)
abc_args += " -dff";
run("abc" + abc_args);
}
run("clean"); run("clean");
} }

2
tests/arch/machxo2/lutram.ys
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@ -11,7 +11,7 @@ sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs mite
design -load postopt design -load postopt
cd lutram_1w1r cd lutram_1w1r
select -assert-count 20 t:LUT4 select -assert-count 28 t:LUT4
select -assert-count 8 t:TRELLIS_DPR16X4 select -assert-count 8 t:TRELLIS_DPR16X4
select -assert-count 8 t:TRELLIS_FF select -assert-count 8 t:TRELLIS_FF
select -assert-none t:LUT4 t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D select -assert-none t:LUT4 t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D

6
tests/arch/machxo2/mux.ys
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@ -15,7 +15,7 @@ proc
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module cd mux4 # Constrain all select calls below inside the top module
select -assert-count 2 t:LUT4 select -assert-count 3 t:LUT4
select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
@ -25,7 +25,7 @@ proc
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module cd mux8 # Constrain all select calls below inside the top module
select -assert-count 5 t:LUT4 select -assert-count 6 t:LUT4
select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
@ -35,6 +35,6 @@ proc
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module cd mux16 # Constrain all select calls below inside the top module
select -assert-max 12 t:LUT4 select -assert-max 13 t:LUT4
select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D

10
tests/arch/nexus/add_sub.ys
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@ -1,21 +1,11 @@
read_verilog ../common/add_sub.v read_verilog ../common/add_sub.v
hierarchy -top top hierarchy -top top
proc proc
design -save orig
equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd top # Constrain all select calls below inside the top module
stat stat
select -assert-count 10 t:LUT4
select -assert-none t:IB t:OB t:VLO t:LUT4 %% t:* %D
design -load orig
equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus -abc9 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 6 t:LUT4 select -assert-count 6 t:LUT4
select -assert-count 4 t:WIDEFN9 select -assert-count 4 t:WIDEFN9
select -assert-none t:IB t:OB t:VLO t:LUT4 t:WIDEFN9 %% t:* %D select -assert-none t:IB t:OB t:VLO t:LUT4 t:WIDEFN9 %% t:* %D

3
tests/arch/nexus/counter.ys
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@ -6,6 +6,7 @@ equiv_opt -assert -multiclock -map +/nexus/cells_sim.v synth_nexus # equivalency
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd top # Constrain all select calls below inside the top module
stat stat
select -assert-count 1 t:INV
select -assert-count 5 t:CCU2 select -assert-count 5 t:CCU2
select -assert-count 8 t:FD1P3DX select -assert-count 8 t:FD1P3DX
select -assert-none t:CCU2 t:FD1P3DX t:IB t:OB t:VLO t:VHI %% t:* %D select -assert-none t:INV t:CCU2 t:FD1P3DX t:IB t:OB t:VLO t:VHI %% t:* %D

2
tests/arch/nexus/logic.ys
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@ -4,5 +4,5 @@ proc
equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd top # Constrain all select calls below inside the top module
select -assert-count 8 t:LUT4 select -assert-count 5 t:LUT4
select -assert-none t:LUT4 t:INV t:IB t:OB t:VLO t:VHI %% t:* %D select -assert-none t:LUT4 t:INV t:IB t:OB t:VLO t:VHI %% t:* %D