Use read_techlib where applicable in tests

tests/arch/analogdevices/dsp_abc9.ys

@@ -25,7 +25,7 @@ select -assert-count 0 t:* t:$mul %D
 
 
 design -reset
-read_verilog -icells -formal <<EOT
+read_techlib -icells -formal <<EOT
 module top(output [43:0] P);
 \$__MUL22X22 mul (.A(42), .B(42), .Y(P));
 assert property (P == 42*42);

tests/arch/analogdevices/opt_lut_ins.ys

@@ -18,7 +18,7 @@ end
 
 EOF
 
-read_verilog -lib +/analogdevices/cells_sim.v
+read_techlib -lib +/analogdevices/cells_sim.v
 equiv_opt -assert -map +/analogdevices/cells_sim.v opt_lut_ins -tech analogdevices
 
 design -load postopt

tests/arch/ecp5/bug2731.ys

@@ -1,4 +1,4 @@
-read_verilog -icells <<EOF
+read_techlib -icells <<EOF
 module top(input c, r, input [1:0] d, output reg [1:0] q);
 TRELLIS_FF #(.REGSET("SET")) ff1(.CLK(c), .LSR(r), .DI(d[0]), .Q(q[0]));
 TRELLIS_FF #(.REGSET("SET")) ff2(.CLK(c), .LSR(r), .DI(d[1]), .Q(q[1]));

tests/arch/ecp5/opt_lut_ins.ys

@@ -21,7 +21,7 @@ end
 
 EOF
 
-read_verilog -lib +/ecp5/cells_sim.v
+read_techlib -lib +/ecp5/cells_sim.v
 
 equiv_opt -assert -map +/ecp5/cells_sim.v opt_lut_ins -tech lattice
 

tests/arch/gowin/init.ys

@@ -1,5 +1,5 @@
 read_verilog init.v
-read_verilog -lib -specify +/gowin/cells_sim.v
+read_techlib -lib -specify +/gowin/cells_sim.v
 design -save read
 
 proc

tests/arch/ice40/bug1597.ys

@@ -67,7 +67,7 @@ module SSCounter6o (input wire rst, clk, adv, jmp, input wire [5:0] in, output w
     SB_LUT4 #(.LUT_INIT(16'h8BB8)) l5 (lo[5], in[5], jmp, out[5], co[4]);
 endmodule
 EOT
-read_verilog -lib +/ice40/cells_sim.v
+read_techlib -lib +/ice40/cells_sim.v
 hierarchy -top top
 flatten
 equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40

tests/arch/ice40/ice40_dsp.ys

@@ -8,5 +8,5 @@ assign o4 = a * b;
 SB_MAC16 m3 (.A(a), .B(b), .O(o5));
 endmodule
 EOT
-read_verilog -lib +/ice40/cells_sim.v
+read_techlib -lib +/ice40/cells_sim.v
 ice40_dsp

tests/arch/ice40/ice40_opt.ys

@@ -1,4 +1,4 @@
-read_verilog -icells -formal <<EOT
+read_techlib -icells -formal <<EOT
 module top(input CI, I0, output [1:0] CO, output O);
     wire A = 1'b0, B = 1'b0;
 	\$__ICE40_CARRY_WRAPPER #(
@@ -21,7 +21,7 @@ module top(input CI, I0, output [1:0] CO, output O);
 endmodule
 EOT
 
-read_verilog -icells -lib +/ice40/abc9_model.v +/ice40/cells_sim.v
+read_techlib -icells -lib +/ice40/abc9_model.v +/ice40/cells_sim.v
 equiv_opt -assert -map +/ice40/abc9_model.v -map +/ice40/cells_sim.v ice40_opt
 design -load postopt
 select -assert-count 1 t:*
@@ -90,7 +90,7 @@ select -assert-count 1 t:SB_CARRY c:carry %i
 
 
 design -reset
-read_verilog -icells <<EOT
+read_techlib -icells <<EOT
 module top(input I3, I2, I1, I0, output O, O2);
 	SB_LUT4 #(
 		.LUT_INIT(8'b 1001_0110)

tests/arch/nanoxplore/meminit.ys

@@ -6,7 +6,7 @@ prep -rdff
 synth_nanoxplore 
 clean_zerowidth
 select -assert-none t:$mem_v2 t:$mem
-read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v
+read_techlib +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v
 prep
 async2sync
 hierarchy -top top
@@ -21,7 +21,7 @@ prep -rdff
 synth_nanoxplore 
 clean_zerowidth
 select -assert-none t:$mem_v2 t:$mem
-read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v
+read_techlib +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v
 prep
 async2sync
 hierarchy -top top
@@ -37,7 +37,7 @@ prep -rdff
 synth_nanoxplore 
 clean_zerowidth
 select -assert-none t:$mem_v2 t:$mem
-read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v
+read_techlib +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v
 prep
 async2sync
 hierarchy -top top

tests/arch/quicklogic/qlf_k6n10f/dsp.ys

@@ -114,7 +114,7 @@ always @(posedge clk) begin
 end
 endmodule
 EOF
-read_verilog +/quicklogic/qlf_k6n10f/dsp_sim.v
+read_techlib +/quicklogic/qlf_k6n10f/dsp_sim.v
 hierarchy -top testbench
 proc
 async2sync

tests/arch/quicklogic/qlf_k6n10f/meminit.ys

@@ -8,7 +8,7 @@ select -assert-none t:$mem_v2 t:$mem
 select -assert-count 1 t:TDP36K
 select -assert-count 1 t:TDP36K a:is_split=0 %i
 select -assert-count 1 t:TDP36K a:was_split_candidate=0 %i
-read_verilog +/quicklogic/common/cells_sim.v +/quicklogic/qlf_k6n10f/cells_sim.v +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
+read_techlib +/quicklogic/common/cells_sim.v +/quicklogic/qlf_k6n10f/cells_sim.v +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
 prep
 async2sync
 hierarchy -top top

tests/arch/xilinx/abc9_dff.ys

@@ -13,7 +13,7 @@ FDCE_1 #(.INIT(0)) fd7(.C(C), .CE(1'b1), .D(D), .CLR(1'b1), .Q(Q[6]));
 FDPE_1 #(.INIT(0)) fd8(.C(C), .CE(1'b1), .D(D), .PRE(1'b1), .Q(Q[7]));
 endmodule
 EOT
-read_verilog -lib +/xilinx/cells_sim.v
+read_techlib -lib +/xilinx/cells_sim.v
 equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
 design -load postopt
 select -assert-count 6 t:FD*
@@ -33,7 +33,7 @@ FDCE_1 #(.INIT(0)) fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6]));
 FDPE_1 #(.INIT(0)) fd8(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[7]));
 endmodule
 EOT
-read_verilog -lib +/xilinx/cells_sim.v
+read_techlib -lib +/xilinx/cells_sim.v
 equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
 design -load postopt
 select -assert-count 4 t:FD*
@@ -57,7 +57,7 @@ logger -expect warning "Whitebox '\$paramod\\FDRE\\INIT=.*1' with \(\* abc9_flop
 logger -expect warning "Whitebox '\$paramod\\FDRE_1\\INIT=.*1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
 logger -expect warning "Whitebox 'FDSE' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
 logger -expect warning "Whitebox '\$paramod\\FDSE_1\\INIT=.*1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
-read_verilog -lib +/xilinx/cells_sim.v
+read_techlib -lib +/xilinx/cells_sim.v
 equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
 design -load postopt
 select -assert-count 8 t:FD*
@@ -79,7 +79,7 @@ always @(posedge clk or posedge pre)
 endmodule
 EOT
 proc
-read_verilog -lib +/xilinx/cells_sim.v
+read_techlib -lib +/xilinx/cells_sim.v
 equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
 design -load postopt
 select -assert-count 1 t:FDCE
@@ -99,7 +99,7 @@ assign q = ~r;
 endmodule
 EOT
 proc
-read_verilog -lib +/xilinx/cells_sim.v
+read_techlib -lib +/xilinx/cells_sim.v
 equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
 design -load postopt
 select -assert-count 1 t:FDRE %co w:r %i
@@ -117,7 +117,7 @@ assign q2 = r;
 endmodule
 EOT
 proc
-read_verilog -lib +/xilinx/cells_sim.v
+read_techlib -lib +/xilinx/cells_sim.v
 equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
 design -load postopt
 select -assert-count 1 t:FDRE %co %a w:r %i
@@ -135,7 +135,7 @@ assign o = r1 | r2;
 endmodule
 EOT
 proc
-read_verilog -lib +/xilinx/cells_sim.v
+read_techlib -lib +/xilinx/cells_sim.v
 equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
 
 

tests/arch/xilinx/bug3670.ys

@@ -1,3 +1,3 @@
 read_verilog bug3670.v
-read_verilog -lib -specify +/xilinx/cells_sim.v
+read_techlib -lib -specify +/xilinx/cells_sim.v
 abc9

tests/arch/xilinx/dsp_abc9.ys

@@ -25,7 +25,7 @@ select -assert-count 0 t:* t:$mul %D
 
 
 design -reset
-read_verilog -icells -formal <<EOT
+read_techlib -icells -formal <<EOT
 module top(output [42:0] P);
 \$__MUL25X18 mul (.A(42), .B(42), .Y(P));
 assert property (P == 42*42);

tests/arch/xilinx/opt_lut_ins.ys

@@ -18,7 +18,7 @@ end
 
 EOF
 
-read_verilog -lib +/xilinx/cells_sim.v
+read_techlib -lib +/xilinx/cells_sim.v
 equiv_opt -assert -map +/xilinx/cells_sim.v opt_lut_ins -tech xilinx
 
 design -load postopt

tests/arch/xilinx/pmgen_xilinx_srl.ys

@@ -1,4 +1,4 @@
-read_verilog -icells <<EOT
+read_techlib -icells <<EOT
 module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, output SO);
   parameter DEPTH = 2;
   parameter [DEPTH-1:0] INIT = 0;
@@ -20,7 +20,7 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
   assign SO = r[DEPTH-1];
 endmodule
 EOT
-read_verilog +/xilinx/cells_sim.v
+read_techlib +/xilinx/cells_sim.v
 proc
 design -save model
 

tests/arch/xilinx/xilinx_dffopt.ys

@@ -18,7 +18,7 @@ FDRE ff (.D(tmp[0]), .CE(tmp[1]), .R(tmp[2]), .Q(o[0]));
 endmodule
 
 EOT
-read_verilog -lib +/xilinx/cells_sim.v
+read_techlib -lib +/xilinx/cells_sim.v
 design -save t0
 
 equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt
@@ -66,7 +66,7 @@ endmodule
 
 EOT
 
-read_verilog -lib +/xilinx/cells_sim.v
+read_techlib -lib +/xilinx/cells_sim.v
 design -save t0
 
 equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt
@@ -114,7 +114,7 @@ endmodule
 
 EOT
 
-read_verilog -lib +/xilinx/cells_sim.v
+read_techlib -lib +/xilinx/cells_sim.v
 design -save t0
 
 equiv_opt -async2sync -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt
@@ -150,7 +150,7 @@ endmodule
 
 EOT
 
-read_verilog -lib +/xilinx/cells_sim.v
+read_techlib -lib +/xilinx/cells_sim.v
 design -save t0
 
 equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt
@@ -198,7 +198,7 @@ endmodule
 
 EOT
 
-read_verilog -lib +/xilinx/cells_sim.v
+read_techlib -lib +/xilinx/cells_sim.v
 design -save t0
 
 equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt
@@ -245,7 +245,7 @@ endmodule
 
 EOT
 
-read_verilog -lib +/xilinx/cells_sim.v
+read_techlib -lib +/xilinx/cells_sim.v
 design -save t0
 
 equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt

tests/arch/xilinx/xilinx_dsp.ys

@@ -8,5 +8,5 @@ assign o4 = a * b;
 DSP48E1 m3 (.A(a), .B(b), .P(o5));
 endmodule
 EOT
-read_verilog -lib +/xilinx/cells_sim.v
+read_techlib -lib +/xilinx/cells_sim.v
 xilinx_dsp