luke
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

delete module frontend

This commit is contained in:
Stan Lee 2026-04-28 15:12:50 -07:00
parent b56104ada2
commit e801ea4fdb
1 changed files with 17 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
frontends/verific/verific.cc
View File

@ -47,6 +47,7 @@ USING_YOSYS_NAMESPACE
#include "Array.h" #include "Array.h"
#include "RuntimeFlags.h" #include "RuntimeFlags.h"
#include "Set.h"
#ifdef VERIFIC_HIER_TREE_SUPPORT #ifdef VERIFIC_HIER_TREE_SUPPORT
#include "hier_tree.h" #include "hier_tree.h"
#endif #endif
@ -3924,6 +3925,22 @@ struct VerificPass : public Pass {
goto check_error; goto check_error;
} }
if (GetSize(args) > argidx && args[argidx] == "-delete_module") {
string lib = "work";
Set *ignored = veri_file::GetIgnoredModuleSet();
for (argidx++; argidx < GetSize(args); argidx++) {
if (args[argidx] == "-work" && argidx+1 < GetSize(args)) {
lib = args[++argidx];
continue;
}
const char *name = args[argidx].c_str();
if (ignored)
ignored->Remove(name);
veri_file::RemoveModule(name, lib.c_str());
}
goto check_error;
}
if (GetSize(args) > argidx && args[argidx] == "-set_vhdl_default_library_path") { if (GetSize(args) > argidx && args[argidx] == "-set_vhdl_default_library_path") {
for (argidx++; argidx < GetSize(args); argidx++) { for (argidx++; argidx < GetSize(args); argidx++) {
#ifdef VERIFIC_VHDL_SUPPORT #ifdef VERIFIC_VHDL_SUPPORT