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Merge pull request #157 from Silimate/pmux2shiftx

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Akash Levy 2026-04-25 09:40:04 -07:00 committed by GitHub
parent 65aad25a61 fe4434b105
commit b56104ada2
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GPG Key ID: B5690EEEBB952194
1 changed files with 6 additions and 6 deletions
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12
passes/opt/pmux2shiftx.cc
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@ -680,9 +680,9 @@ struct Pmux2ShiftxPass : public Pass {
// creat cmp signal
SigSpec cmp = perm_sig;
if (perm_xormask.as_bool())
cmp = module->Xor(NEW_ID, cmp, perm_xormask, false, src);
cmp = module->Xor(NEW_ID2_SUFFIX("xor"), cmp, perm_xormask, false, src);
if (offset.as_bool())
cmp = module->Sub(NEW_ID, cmp, offset, false, src);
cmp = module->Sub(NEW_ID2_SUFFIX("sub"), cmp, offset, false, src);
// create enable signal
SigBit en = State::S1;
@ -690,8 +690,8 @@ struct Pmux2ShiftxPass : public Pass {
Const enable_mask(State::S0, max_choice+1);
for (auto &it : perm_choices)
enable_mask.set(it.first.as_int(), State::S1);
en = module->addWire(NEW_ID);
module->addShift(NEW_ID, enable_mask, cmp, en, false, src);
en = module->addWire(NEW_ID2_SUFFIX("en"));
module->addShift(NEW_ID2_SUFFIX("shift"), enable_mask, cmp, en, false, src);
}
// create data signal
@ -710,8 +710,8 @@ struct Pmux2ShiftxPass : public Pass {
// create shiftx cell
SigSpec shifted_cmp = {cmp, SigSpec(State::S0, width_bits)};
SigSpec outsig = module->addWire(NEW_ID, width);
Cell *c = module->addShiftx(NEW_ID, data, shifted_cmp, outsig, false, src);
SigSpec outsig = module->addWire(NEW_ID2_SUFFIX("out"), width);
Cell *c = module->addShiftx(NEW_ID2_SUFFIX("shiftx"), data, shifted_cmp, outsig, false, src);
updated_S.append(en);
updated_B.append(outsig);
log(" created $shiftx cell %s.\n", log_id(c));