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Merge 77b63be4d2 into 8eb3133076

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nella 2026-06-11 09:27:44 +02:00 committed by GitHub
parent 8eb3133076 77b63be4d2
commit e76778bf63
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13 changed files with 336 additions and 0 deletions
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13
tests/techmap/abc_new_abc_verify_pass.ys Normal file
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read_verilog <<EOT
module top(input a, input b, output y);
assign y = a & b;
endmodule
EOT
hierarchy -check -top top
proc; opt -fast
logger -expect log "ABC: .*i/o = +2/ +1" 2
logger -expect log "ABC: Warning: The network is combinational\." 1
logger -expect log "ABC: Networks are equivalent\." 1
logger -expect error "Found 1 problems in 'check -assert'" 1
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
check -assert

63
tests/techmap/abc_new_basic_gates.ys Normal file
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design -reset
read_verilog <<EOT
module top(input a, input b, output y);
assign y = a | b;
endmodule
EOT
hierarchy -check -top top
proc; opt -fast
logger -expect log "ABC: .*i/o = +2/ +1" 2
logger -expect log "ABC: Warning: The network is combinational\." 1
logger -expect log "ABC: Networks are equivalent\." 1
logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver\." 1
logger -expect error "Found 1 problems in 'check -assert'" 1
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
check -assert
design -reset
read_verilog <<EOT
module top(input a, input b, output y);
assign y = ~(a & b);
endmodule
EOT
hierarchy -check -top top
proc; opt -fast
logger -expect log "ABC: .*i/o = +2/ +1" 2
logger -expect log "ABC: Warning: The network is combinational\." 1
logger -expect log "ABC: Networks are equivalent\." 1
logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver\." 1
logger -expect error "Found 1 problems in 'check -assert'" 1
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
check -assert
design -reset
read_verilog <<EOT
module top(input a, input b, output y);
assign y = a ^ b;
endmodule
EOT
hierarchy -check -top top
proc; opt -fast
logger -expect log "ABC: .*i/o = +2/ +1" 2
logger -expect log "ABC: Warning: The network is combinational\." 1
logger -expect log "ABC: Networks are equivalent\." 1
logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver\." 1
logger -expect error "Found 1 problems in 'check -assert'" 1
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
check -assert
design -reset
read_verilog <<EOT
module top(input a, input b, input c, input d, output y);
assign y = (a & b) | (c & d);
endmodule
EOT
hierarchy -check -top top
proc; opt -fast
logger -expect log "ABC: .*i/o = +4/ +1" 2
logger -expect log "ABC: Warning: The network is combinational\." 1
logger -expect log "ABC: Networks are equivalent\." 1
logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver\." 1
logger -expect error "Found 1 problems in 'check -assert'" 1
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
check -assert

18
tests/techmap/abc_new_box.ys Normal file
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read_verilog -icells -specify <<EOT
(* abc9_box, blackbox *)
module box1(input i, output o);
specify
(i => o) = 1;
endspecify
endmodule
module top(input a, input b, output o);
wire z;
$_AND_ gate(.A(a), .B(b), .Y(o));
box1 u_box(.i(a), .o(z));
endmodule
EOT
hierarchy -check -top top
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
select -assert-min 1 t:*

14
tests/techmap/abc_new_equiv_opt.ys Normal file
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read_verilog <<EOT
module top(input a, input b, input c, output y, output z);
assign y = ~(a & b);
assign z = ~(a | c);
endmodule
EOT
hierarchy -check -top top
proc; opt -fast
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
select -assert-min 1 t:NAND
select -assert-min 1 t:NOR
select -assert-min 1 t:NAND t:NOT t:NOR t:BUF %u
select -assert-none t:$_AND_ t:$_OR_ t:$_NAND_ t:$_NOR_ %u

14
tests/techmap/abc_new_experimental_sentinel.ys Normal file
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read_verilog <<EOT
module top(input a, output y); assign y = a; endmodule
EOT
hierarchy -check -top top
proc; opt -fast
logger -expect log "ABC: .*i/o = +1/ +1" 3
logger -expect log "ABC: Warning: The network is combinational\." 1
logger -expect warning "Feature 'abc_new' is experimental" 1
logger -expect warning "Feature 'write_xaiger2' is experimental" 1
logger -expect warning "Feature 'read_xaiger2' is experimental" 1
logger -expect error "Missing mapping \(no 'M' section\)" 1
abc_new -liberty ../../examples/cmos/cmos_cells.lib

12
tests/techmap/abc_new_keep.ys Normal file
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read_verilog <<EOT
module top(input a, input b, output o);
(* keep *) wire w = a & b;
assign o = ~w;
endmodule
EOT
hierarchy -check -top top
proc; opt -fast; techmap
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
select -assert-none t:$_AND_
select -assert-min 1 t:NAND t:NOT t:NOR t:BUF %u

63
tests/techmap/abc_new_multibit.ys Normal file
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design -reset
read_verilog <<EOT
module top(input [7:0] a, input [7:0] b, output [7:0] y);
assign y = a & b;
endmodule
EOT
hierarchy -check -top top
proc; opt -fast
logger -expect log "ABC: .*i/o = +16/ +8" 2
logger -expect log "ABC: Warning: The network is combinational\." 1
logger -expect log "ABC: Networks are equivalent\." 1
logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver\." 8
logger -expect error "Found 8 problems in 'check -assert'" 1
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
check -assert
design -reset
read_verilog <<EOT
module top(input [3:0] a, input [3:0] b, output [3:0] y);
assign y = a ^ b;
endmodule
EOT
hierarchy -check -top top
proc; opt -fast
logger -expect log "ABC: .*i/o = +8/ +4" 2
logger -expect log "ABC: Warning: The network is combinational\." 1
logger -expect log "ABC: Networks are equivalent\." 1
logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver\." 4
logger -expect error "Found 4 problems in 'check -assert'" 1
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
check -assert
design -reset
read_verilog <<EOT
module top(input [7:0] a, output y);
assign y = &a;
endmodule
EOT
hierarchy -check -top top
proc; opt -fast
logger -expect log "ABC: .*i/o = +8/ +1" 2
logger -expect log "ABC: Warning: The network is combinational\." 1
logger -expect log "ABC: Networks are equivalent\." 1
logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver\." 1
logger -expect error "Found 1 problems in 'check -assert'" 1
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
check -assert
design -reset
read_verilog <<EOT
module top(input [3:0] a, input [3:0] b, output [3:0] sum, output cout);
assign {cout, sum} = a + b;
endmodule
EOT
hierarchy -check -top top
proc; opt -fast
logger -expect log "ABC: .*i/o = +8/ +5" 2
logger -expect log "ABC: Warning: The network is combinational\." 1
logger -expect log "ABC: Networks are equivalent\." 1
logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver\." 5
logger -expect error "Found 5 problems in 'check -assert'" 1
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
check -assert

14
tests/techmap/abc_new_multibit_undriven.ys Normal file
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read_verilog <<EOT
module top(input [3:0] a, output [3:0] y);
assign y = ~a;
endmodule
EOT
hierarchy -check -top top
proc; opt -fast
logger -expect log "ABC: .*i/o = +4/ +4" 2
logger -expect log "ABC: Warning: The network is combinational\." 1
logger -expect log "ABC: Networks are equivalent\." 1
logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver" 4
logger -expect error "Found 4 problems in 'check -assert'" 1
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
check -assert

65
tests/techmap/abc_new_mux.ys Normal file
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design -reset
read_verilog <<EOT
module top(input a, input b, input sel, output y);
assign y = sel ? a : b;
endmodule
EOT
hierarchy -check -top top
proc; opt -fast
logger -expect log "ABC: .*i/o = +3/ +1" 2
logger -expect log "ABC: Warning: The network is combinational\." 1
logger -expect log "ABC: Networks are equivalent\." 1
logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver\." 1
logger -expect error "Found 1 problems in 'check -assert'" 1
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
check -assert
design -reset
read_verilog <<EOT
module top(input [3:0] data, input [1:0] sel, output y);
assign y = data[sel];
endmodule
EOT
hierarchy -check -top top
proc; opt -fast
logger -expect log "ABC: .*i/o = +6/ +1" 2
logger -expect log "ABC: Warning: The network is combinational\." 1
logger -expect log "ABC: Networks are equivalent\." 1
logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver\." 1
logger -expect error "Found 1 problems in 'check -assert'" 1
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
check -assert
design -reset
read_verilog <<EOT
module top(input a, input b, input c, input s1, input s2, output y);
wire temp;
assign temp = s1 ? a : b;
assign y = s2 ? temp : c;
endmodule
EOT
hierarchy -check -top top
proc; opt -fast
logger -expect log "ABC: .*i/o = +5/ +1" 2
logger -expect log "ABC: Warning: The network is combinational\." 1
logger -expect log "ABC: Networks are equivalent\." 1
logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver\." 1
logger -expect error "Found 1 problems in 'check -assert'" 1
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
check -assert
design -reset
read_verilog <<EOT
module top(input [2:0] a, output [1:0] y);
assign y = a[2] ? 2'b11 : a[1] ? 2'b10 : a[0] ? 2'b01 : 2'b00;
endmodule
EOT
hierarchy -check -top top
proc; opt -fast
logger -expect log "ABC: .*i/o = +3/ +2" 2
logger -expect log "ABC: Warning: The network is combinational\." 1
logger -expect log "ABC: Networks are equivalent\." 1
logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver\." 2
logger -expect error "Found 2 problems in 'check -assert'" 1
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
check -assert

11
tests/techmap/abc_new_no_script.ys Normal file
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read_verilog <<EOT
module top(input [3:0] a, input [3:0] b, output [3:0] y);
assign y = a & b;
endmodule
EOT
hierarchy -check -top top
proc; opt -fast
logger -expect log "ABC: .*i/o = +8/ +4" 3
logger -expect log "ABC: Warning: The network is combinational\." 1
logger -expect error "Missing mapping \(no 'M' section\)" 1
abc_new -liberty ../../examples/cmos/cmos_cells.lib

17
tests/techmap/abc_new_sc_undriven_wire.ys Normal file
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read_verilog <<EOT
module top(input a, input b, output y);
assign y = a & b;
endmodule
EOT
hierarchy -check -top top
proc; opt -fast
logger -expect warning "Feature 'abc_new' is experimental" 1
logger -expect warning "Feature 'write_xaiger2' is experimental" 1
logger -expect warning "Feature 'read_xaiger2' is experimental" 1
logger -expect log "ABC: .*i/o = +2/ +1" 2
logger -expect log "ABC: Warning: The network is combinational\." 1
logger -expect log "ABC: Networks are equivalent\." 1
logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver\." 1
logger -expect error "Found 1 problems in 'check -assert'" 1
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
check -assert

17
tests/techmap/abc_new_sc_verify_fails.ys Normal file
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read_verilog <<EOT
module top(input a, input b, output y);
assign y = a & b;
endmodule
EOT
hierarchy -check -top top
proc; opt -fast
logger -expect warning "Feature 'abc_new' is experimental" 1
logger -expect warning "Feature 'write_xaiger2' is experimental" 1
logger -expect warning "Feature 'read_xaiger2' is experimental" 1
logger -expect log "ABC: .*i/o = +2/ +1" 2
logger -expect log "ABC: Warning: The network is combinational\." 1
logger -expect log "ABC: Networks are equivalent\." 1
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver\." 1
logger -expect error "Found 1 problems in 'check -assert'" 1
check -assert

15
tests/techmap/abc_new_sequential.ys Normal file
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read_verilog <<EOT
module top(input clk, input a, input b, output reg y);
always @(posedge clk) y <= a & b;
endmodule
EOT
hierarchy -check -top top
proc; opt -fast
dfflibmap -liberty ../../examples/cmos/cmos_cells.lib
logger -expect log "ABC: .*i/o = +4/ +3" 2
logger -expect log "ABC: Warning: The network is combinational\." 1
logger -expect log "ABC: Networks are equivalent\." 1
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
logger -expect error "Found 1 problems in 'check -assert'" 1
check -assert