mirror of https://github.com/YosysHQ/yosys.git
15 lines
440 B
Plaintext
15 lines
440 B
Plaintext
read_verilog <<EOT
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module top(input a, input b, input c, output y, output z);
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assign y = ~(a & b);
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assign z = ~(a | c);
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endmodule
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EOT
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hierarchy -check -top top
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proc; opt -fast
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abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
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select -assert-min 1 t:NAND
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select -assert-min 1 t:NOR
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select -assert-min 1 t:NAND t:NOT t:NOR t:BUF %u
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select -assert-none t:$_AND_ t:$_OR_ t:$_NAND_ t:$_NOR_ %u
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