luke/yosys
1
0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 01:53:53 +02:00
Code Issues Packages Projects Releases Wiki Activity

rtlil: remove SigSpec::parse fallback that isn't necessary with content hashing

Browse Source
This commit is contained in:
Emil J. Tywoniak
2026-10-02 18:42:02 +02:00
parent 11f4b1b7ad
commit e141bf4aa6
1 changed files with 4 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files
kernel/rtlil.cc
+4 -15
View File
@@ -5750,19 +5750,9 @@ static void sigspec_parse_split(std::vector<std::string> &tokens, const std::str
tokens.push_back(text.substr(start));
}
static RTLIL::Wire *sigspec_parse_wire(RTLIL::Module *module,
std::optional<dict<std::string, RTLIL::Wire*>> &wires_by_name, const std::string &netname)
static RTLIL::Wire *sigspec_parse_wire(RTLIL::Module *module, const std::string &netname)
{
if (RTLIL::Wire *wire = module->wire(module->twines().find(netname)))
return wire;
if (!wires_by_name) {
wires_by_name.emplace();
for (auto wire : module->wires())
wires_by_name->emplace(wire->name.str(), wire);
}
auto it = wires_by_name->find(netname);
return it == wires_by_name->end() ? nullptr : it->second;
return module->wire(module->twines().find(netname));
}
bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
@@ -5771,7 +5761,6 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
sigspec_parse_split(tokens, str, ',');
sig = RTLIL::SigSpec();
std::optional<dict<std::string, RTLIL::Wire*>> wires_by_name;
for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
{
std::string netname = tokens[tokidx];
@@ -5795,7 +5784,7 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
if (netname[0] != '$' && netname[0] != '\\')
netname = "\\" + netname;
if (sigspec_parse_wire(module, wires_by_name, netname) == nullptr) {
if (sigspec_parse_wire(module, netname) == nullptr) {
size_t indices_pos = netname.size()-1;
if (indices_pos > 2 && netname[indices_pos] == ']')
{
@@ -5812,7 +5801,7 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
}
}
RTLIL::Wire *wire = sigspec_parse_wire(module, wires_by_name, netname);
RTLIL::Wire *wire = sigspec_parse_wire(module, netname);
if (wire == nullptr)
return false;