From d1357f171fe532a1026863db91f0a1c472d873c3 Mon Sep 17 00:00:00 2001
From: Lofty <lofty@yosyshq.com>
Date: Mon, 10 Aug 2026 10:17:31 +0100
Subject: [PATCH] fix handling of multiple modules

Co-authored-by: nella <nella@yosyshq.com>
---
 frontends/aiger/aigerparse.cc | 15 +++++++++------
 tests/techmap/abc_new.ys      | 13 +++++++++++++
 2 files changed, 22 insertions(+), 6 deletions(-)
 create mode 100644 tests/techmap/abc_new.ys

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 460bc50ba..9c635a5a8 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -480,19 +480,22 @@ void AigerReader::parse_xaiger()
 				mapping_cell.type = RTLIL::escape_id(cellName);
 				mapping_cell.out = RTLIL::escape_id(outPinName);
 
-				auto module = design->addModule(RTLIL::escape_id(cellName));
-				module->set_bool_attribute(ID::blackbox);
-				module->addWire(RTLIL::escape_id(outPinName))->port_output = true;
-
 				for (unsigned j = 0; j < inPinNum; ++j) {
 					auto inPinName = std::string{};
 					std::getline(f, inPinName, '\0');
 					log_debug2("M:    inPinName=%s\n", inPinName);
 					mapping_cell.ins.push_back(RTLIL::escape_id(inPinName));
-					module->addWire(RTLIL::escape_id(inPinName))->port_input = true;
 				}
 
-				module->fixup_ports();
+				if (!design->module(mapping_cell.type)) {
+					auto module = design->addModule(mapping_cell.type);
+					module->set_bool_attribute(ID::blackbox);
+					module->addWire(mapping_cell.out)->port_output = true;
+					for (unsigned j = 0; j < inPinNum; ++j) {
+						module->addWire(mapping_cell.ins.at(j))->port_input = true;
+					}
+					module->fixup_ports();
+				}
 
 				mapping_cells.push_back(std::move(mapping_cell));
 			}
diff --git a/tests/techmap/abc_new.ys b/tests/techmap/abc_new.ys
new file mode 100644
index 000000000..9c70606ea
--- /dev/null
+++ b/tests/techmap/abc_new.ys
@@ -0,0 +1,13 @@
+read_verilog <<EOT
+module sub(input a, b, c, output y);
+  assign y = (a & b) | c;
+endmodule
+module top(input a, b, c, d, output y, z);
+  assign z = (a ^ b) & d;
+  sub s_i (.a(a), .b(b), .c(c), .y(y));
+endmodule
+EOT
+hierarchy -top top
+techmap
+abc_new -liberty ../liberty/normal.lib -liberty ../liberty/dff.lib
+