From cc4c9c4eba97e8727e5236d012c516c8fc3a3b24 Mon Sep 17 00:00:00 2001
From: William Zhu <williamzhu@Williams-MacBook-Pro.local>
Date: Thu, 27 Mar 2025 12:31:37 -0700
Subject: [PATCH] first tests for opt_expand

---
 Makefile                     |   1 +
 tests/silimate/opt_expand.ys | 225 +++++++++++++++++++++++++++++++++++
 tests/silimate/run-test.sh   |   6 +
 3 files changed, 232 insertions(+)
 create mode 100644 tests/silimate/opt_expand.ys
 create mode 100755 tests/silimate/run-test.sh

diff --git a/Makefile b/Makefile
index ec01e3394..132a872e2 100644
--- a/Makefile
+++ b/Makefile
@@ -946,6 +946,7 @@ SH_TEST_DIRS += tests/blif
 SH_TEST_DIRS += tests/memfile
 SH_TEST_DIRS += tests/fmt
 # SH_TEST_DIRS += tests/cxxrtl
+SH_TEST_DIRS += tests/silimate
 ifeq ($(ENABLE_FUNCTIONAL_TESTS),1)
 SH_TEST_DIRS += tests/functional
 endif
diff --git a/tests/silimate/opt_expand.ys b/tests/silimate/opt_expand.ys
new file mode 100644
index 000000000..d56078f1e
--- /dev/null
+++ b/tests/silimate/opt_expand.ys
@@ -0,0 +1,225 @@
+log -header "Simple positive case"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire a,
+  input wire b,
+  input wire c,
+  output wire x
+);
+  wire m;
+
+  assign m = a | b;
+  assign x = m & c;
+endmodule
+EOF
+check -assert
+equiv_opt -assert opt_expand
+design -load postopt
+select -assert-count 2 t:$and
+select -assert-count 1 t:$or
+design -reset
+log -pop
+
+
+
+log -header "No intermediate wire: (a | b) & c"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire a,
+  input wire b,
+  input wire c,
+  output wire x
+);
+  assign x = (a | b) & c;
+endmodule
+EOF
+check -assert
+equiv_opt -assert opt_expand
+design -load postopt
+select -assert-count 2 t:$and
+select -assert-count 1 t:$or
+
+design -reset
+log -pop
+
+
+
+log -header "No intermediate wire flipped: c & (a | b)"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire a,
+  input wire b,
+  input wire c,
+  output wire x
+);
+  assign x = c & (a | b);
+endmodule
+EOF
+check -assert
+equiv_opt -assert opt_expand
+design -load postopt
+select -assert-count 2 t:$and
+select -assert-count 1 t:$or
+
+design -reset
+log -pop
+
+
+
+log -header "Fanout from intermediate wire"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire a,
+  input wire b,
+  input wire c,
+  output wire m,
+  output wire x
+);
+  assign m = a | b;
+  assign x = c & m;
+
+endmodule
+EOF
+check -assert
+equiv_opt -assert opt_expand
+design -load postopt
+select -assert-count 1 t:$and
+select -assert-count 1 t:$or
+
+design -reset
+log -pop
+
+
+
+log -header "Nested AND gate: ((a & b) | c) & d"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire a,
+  input wire b,
+  input wire c,
+  input wire d,
+  output wire x
+);
+  assign x = ((a & b) | c) & d;
+endmodule
+EOF
+check -assert
+equiv_opt -assert opt_expand
+design -load postopt
+select -assert-count 3 t:$and
+select -assert-count 1 t:$or
+
+design -reset
+log -pop
+
+
+
+log -header "Nested OR gate: ((a | b) | c) & d"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire a,
+  input wire b,
+  input wire c,
+  input wire d,
+  output wire x
+);
+  assign x = ((a | b) | c) & d;
+endmodule
+EOF
+check -assert
+equiv_opt -assert opt_expand
+design -load postopt
+select -assert-count 3 t:$and
+select -assert-count 2 t:$or
+
+design -reset
+log -pop
+
+
+
+log -header "With inverter: (~a | b) & c"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire a,
+  input wire b,
+  input wire c,
+  output wire x
+);
+  assign x = (~a | b) & c;
+endmodule
+EOF
+check -assert
+equiv_opt -assert opt_expand
+design -load postopt
+select -assert-count 2 t:$and
+select -assert-count 1 t:$or
+
+design -reset
+log -pop
+
+
+
+log -header "Deeper nesting: ((a | b) & (c | d)) & e"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire a,
+  input wire b,
+  input wire c,
+  input wire d,
+  input wire e,
+  output wire x
+);
+  assign x = ((a | b) & (c | d)) & e;
+endmodule
+EOF
+check -assert
+equiv_opt -assert opt_expand
+design -load postopt
+select -assert-count 4 t:$and
+select -assert-count 2 t:$or
+
+design -reset
+log -pop
+
+
+
+log -header "More inputs and nesting: ((a | b | c) & (d | e)) & f"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire a,
+  input wire b,
+  input wire c,
+  input wire d,
+  input wire e,
+  input wire f,
+  output wire x
+);
+  assign x = ((a | b | c) & (d | e)) & f;
+endmodule
+EOF
+check -assert
+equiv_opt -assert opt_expand
+design -load postopt
+select -assert-count 4 t:$and
+select -assert-count 3 t:$or
+
+design -reset
+log -pop
\ No newline at end of file
diff --git a/tests/silimate/run-test.sh b/tests/silimate/run-test.sh
new file mode 100755
index 000000000..e9698386e
--- /dev/null
+++ b/tests/silimate/run-test.sh
@@ -0,0 +1,6 @@
+#!/usr/bin/env bash
+set -e
+for x in *.ys; do
+  echo "Running $x.."
+  ../../yosys -ql ${x%.ys}.log $x
+done