diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 9a5ffc767..05b24fe7c 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -257,12 +257,16 @@ bool is_blackbox(Netlist *nl)
 
 RTLIL::IdString VerificImporter::new_verific_id(Verific::DesignObj *obj)
 {
-	return module->uniquify(RTLIL::escape_id(obj->Name()));
+	RTLIL::IdString base = RTLIL::escape_id(obj->Name());
+	int &idx = uniquify_cache[base];
+	return module->uniquify(base, idx);
 }
 
 RTLIL::IdString VerificImporter::new_verific_id_suffix(RTLIL::IdString id, const char *suffix)
 {
-	return module->uniquify(stringf("%s_%s", id, suffix));
+	RTLIL::IdString base = stringf("%s_%s", id, suffix);
+	int &idx = uniquify_cache[base];
+	return module->uniquify(base, idx);
 }
 
 static const RTLIL::Const extract_vhdl_boolean(std::string &val)
@@ -1549,6 +1553,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 	module->name = module_name;
 	design->add(module);
 
+	uniquify_cache.clear();
+
 	if (is_blackbox(nl)) {
 		log("Importing blackbox module %s.\n", RTLIL::id2cstr(module->name));
 		log_flush();
diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h
index 3d7e9c241..2c00e2414 100644
--- a/frontends/verific/verific.h
+++ b/frontends/verific/verific.h
@@ -80,6 +80,8 @@ struct VerificImporter
 	bool mode_gates, mode_keep, mode_nosva, mode_sva_continue, mode_names, mode_verific;
 	bool mode_autocover, mode_fullinit;
 
+	dict<RTLIL::IdString, int> uniquify_cache;
+
 	int num_sva_continue = 0;
 
 	VerificImporter(bool mode_gates, bool mode_keep, bool mode_nosva, bool mode_sva_continue, bool mode_names, bool mode_verific, bool mode_autocover, bool mode_fullinit);