mirror of https://github.com/YosysHQ/yosys.git
added stress tests
This commit is contained in:
williamzhu17
parent
58d903eee6
commit
ba709dc0ed
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@ -824,29 +824,119 @@ log -pop
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# TODO
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log -header "Combinational feedback loop"
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log -header "Stress test"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire [7:0] a0,
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input wire [7:0] a1,
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input wire [7:0] a2,
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output wire y
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);
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wire w0, w1;
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wire c0, c1, c2;
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// Two AND gates feeding each other
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assign w0 = a & w1;
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assign w1 = a & w0;
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// Stage 0
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wire s0_w0 = a0[0] & a0[1];
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wire s0_w1 = a0[2] & a0[3];
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wire s0_w2 = s0_w0 & s0_w1;
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wire s0_w3 = s0_w2 & a0[4];
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wire s0_w4 = a0[0] & a0[5];
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wire s0_w5 = s0_w3 & a0[6];
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wire s0_w6 = s0_w4 & a0[7];
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assign c0 = s0_w5 & s0_w6;
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assign y = w1;
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// Stage 1
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wire s1_w0 = a1[0] & a1[1];
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wire s1_w1 = a1[2] & a1[3];
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wire s1_w2 = s1_w0 & s1_w1;
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wire s1_w3 = s1_w2 & a1[4];
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wire s1_w4 = c0 & a1[5];
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wire s1_w5 = s1_w3 & a1[6];
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wire s1_w6 = s1_w4 & a1[7];
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assign c1 = s1_w5 & s1_w6;
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// Stage 2
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wire s2_w0 = a2[0] & a2[1];
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wire s2_w1 = a2[2] & a2[3];
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wire s2_w2 = s2_w0 & s2_w1;
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wire s2_w3 = s2_w2 & a2[4];
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wire s2_w4 = c1 & a2[5];
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wire s2_w5 = s2_w3 & a2[6];
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wire s2_w6 = s2_w4 & a2[7];
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assign c2 = s2_w5 & s2_w6;
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assign y = c2;
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endmodule
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EOF
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# check -assert
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check -assert
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# Check equivalence after extract_reduce
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# equiv_opt -assert extract_reduce
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extract_reduce -allow-off-chain
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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extract_reduce
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opt_clean
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# Check final design has correct number of gates and inputs
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select -assert-count 0 t:$and
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select -assert-count 1 t:$reduce_and
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design -reset
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log -pop
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log -header "Stress test reconvergence"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] a0,
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input wire [7:0] a1,
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input wire [7:0] a2,
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output wire y
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);
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wire c0, c1, c2;
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// Stage 0
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wire s0_w0 = a0[0] & a0[1];
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wire s0_w1 = a0[2] & a0[3];
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wire s0_w2 = s0_w0 & s0_w1;
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wire s0_w3 = s0_w2 & a0[4];
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wire s0_w4 = s0_w2 & a0[5];
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wire s0_w5 = s0_w3 & a0[6];
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wire s0_w6 = s0_w4 & a0[7];
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assign c0 = s0_w5 & s0_w6;
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// Stage 1
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wire s1_w0 = a1[0] & a1[1];
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wire s1_w1 = a1[2] & a1[3];
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wire s1_w2 = s1_w0 & s1_w1;
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wire s1_w3 = s1_w2 & a1[4];
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wire s1_w4 = s1_w2 & a1[5];
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wire s1_w5 = s1_w3 & a1[6];
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wire s1_w6 = s1_w4 & c0;
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assign c1 = s1_w5 & s1_w6;
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// Stage 2
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wire s2_w0 = a2[0] & a2[1];
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wire s2_w1 = a2[2] & a2[3];
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wire s2_w2 = s2_w0 & s2_w1;
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wire s2_w3 = s2_w2 & a2[4];
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wire s2_w4 = s2_w2 & a2[5];
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wire s2_w5 = s2_w3 & a2[6];
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wire s2_w6 = s2_w4 & c1;
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assign c2 = s2_w5 & s2_w6;
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assign y = c2;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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@ -854,9 +944,7 @@ opt_clean
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# Check final design has correct number of gates and inputs
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select -assert-count 0 t:$and
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select -assert-count 2 t:$reduce_and
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select -assert-count 1 t:$reduce_and r:A_WIDTH=4 %i
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select -assert-count 1 t:$reduce_and r:A_WIDTH=6 %i
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select -assert-count 4 t:$reduce_and
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design -reset
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log -pop
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@ -394,47 +394,191 @@ log -pop
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# TODO check about infinite loop
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log -header "Mux with feedback that causes infinite loop"
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log -header "Stress test"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [2:0] sel,
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input wire [3:0] a,
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input wire [5:0] sel0,
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input wire [5:0] sel1,
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input wire [5:0] sel2,
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input wire [6:0] a0,
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input wire [6:0] a1,
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input wire [6:0] a2,
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output wire x
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);
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wire w0, w1;
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wire x0, x1;
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assign w0 = sel[0] ? a[0] : w0;
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assign w1 = sel[1] ? a[1] : w0;
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assign x = sel[2] ? a[2] : w1;
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// Stage 0
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wire s0_w0 = sel0[0] ? a0[1] : a0[0];
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wire s0_w1 = sel0[1] ? a0[2] : s0_w0;
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wire s0_w2 = sel0[2] ? a0[3] : s0_w1;
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wire s0_w4 = sel0[5] ? a0[4] : a0[5];
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wire s0_w3 = sel0[3] ? s0_w2 : s0_w4;
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assign x0 = sel0[4] ? s0_w3 : a0[6];
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// Stage 1
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wire s1_w0 = sel1[0] ? a1[1] : a1[0];
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wire s1_w1 = sel1[1] ? a1[2] : s1_w0;
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wire s1_w2 = sel1[2] ? a1[3] : s1_w1;
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wire s1_w4 = sel1[5] ? a1[4] : a1[5];
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wire s1_w3 = sel1[3] ? s1_w2 : s1_w4;
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assign x1 = sel1[4] ? s1_w3 : x0;
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// Stage 2
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wire s2_w0 = sel2[0] ? a2[1] : a2[0];
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wire s2_w1 = sel2[1] ? a2[2] : s2_w0;
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wire s2_w2 = sel2[2] ? a2[3] : s2_w1;
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wire s2_w4 = sel2[5] ? a2[4] : a2[5];
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wire s2_w3 = sel2[3] ? s2_w2 : s2_w4;
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assign x = sel2[4] ? s2_w3 : x1;
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endmodule
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EOF
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# check -assert
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autoname
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write_json dump_pre.json
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exec -- netlistsvg dump_pre.json -o dump_pre.svg
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check -assert
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# Check equivalence after extract_reduce
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# equiv_opt -assert extract_reduce
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extract_reduce -allow-off-chain
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean and opt_reduce to remove unnecessary cells
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# design -load postopt
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design -load postopt
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opt_clean
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opt_reduce
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autoname
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write_json dump_post.json
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exec -- netlistsvg dump_post.json -o dump_post.svg
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# Check we got one pmux with correct number of inputs
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select -assert-count 0 t:$mux
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select -assert-count 1 t:$pmux
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design -reset
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log -pop
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log -header "Stress test with reconverging tree and no off chain"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] sel0,
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input wire [7:0] sel1,
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input wire [7:0] sel2,
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input wire [7:0] a0,
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input wire [7:0] a1,
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input wire [7:0] a2,
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output wire x
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);
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wire x0, x1;
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// Stage 0
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wire s0_w6 = sel0[7] ? a0[7] : a0[4];
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wire s0_w4 = sel0[6] ? a0[3] : s0_w6;
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wire s0_w5 = sel0[5] ? a0[5] : s0_w4;
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wire s0_w0 = sel0[0] ? a0[1] : a0[0];
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wire s0_w1 = sel0[1] ? a0[2] : s0_w0;
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wire s0_w2 = sel0[2] ? s0_w4 : s0_w1;
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wire s0_w3 = sel0[3] ? s0_w2 : s0_w5;
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assign x0 = sel0[4] ? a0[6] : s0_w3;
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// Stage 1
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wire s1_w6 = sel1[7] ? a1[7] : a1[4];
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wire s1_w4 = sel1[6] ? a1[3] : s1_w6;
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wire s1_w5 = sel1[5] ? a1[5] : s1_w4;
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wire s1_w0 = sel1[0] ? a1[1] : x0;
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wire s1_w1 = sel1[1] ? a1[2] : s1_w0;
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wire s1_w2 = sel1[2] ? s1_w4 : s1_w1;
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wire s1_w3 = sel1[3] ? s1_w2 : s1_w5;
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assign x1 = sel1[4] ? a1[6] : s1_w3;
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// Stage 2
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wire s2_w6 = sel2[7] ? a2[7] : a2[4];
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wire s2_w4 = sel2[6] ? a2[3] : s2_w6;
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wire s2_w5 = sel2[5] ? a2[5] : s2_w4;
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wire s2_w0 = sel2[0] ? a2[1] : x1;
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wire s2_w1 = sel2[1] ? a2[2] : s2_w0;
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wire s2_w2 = sel2[2] ? s2_w4 : s2_w1;
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wire s2_w3 = sel2[3] ? s2_w2 : s2_w5;
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assign x = sel2[4] ? a2[6] : s2_w3;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean and opt_reduce to remove unnecessary cells
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design -load postopt
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opt_clean
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opt_reduce
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# Check we got one pmux with correct number of inputs
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select -assert-count 0 t:$mux
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select -assert-count 2 t:$pmux
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select -assert-count 1 t:$pmux r:S_WIDTH=3 %i
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select -assert-count 1 t:$pmux r:S_WIDTH=6 %i
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select -assert-count 4 t:$pmux
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design -reset
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log -pop
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log -header "Stress test with reconverging tree and yes off chain"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] sel0,
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input wire [7:0] sel1,
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input wire [7:0] sel2,
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input wire [7:0] a0,
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input wire [7:0] a1,
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input wire [7:0] a2,
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output wire x
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);
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wire x0, x1;
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// Stage 0
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wire s0_w6 = sel0[7] ? a0[7] : a0[4];
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wire s0_w4 = sel0[6] ? a0[3] : s0_w6;
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wire s0_w5 = sel0[5] ? a0[5] : s0_w4;
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wire s0_w0 = sel0[0] ? a0[1] : a0[0];
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wire s0_w1 = sel0[1] ? a0[2] : s0_w0;
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wire s0_w2 = sel0[2] ? s0_w4 : s0_w1;
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wire s0_w3 = sel0[3] ? s0_w2 : s0_w5;
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assign x0 = sel0[4] ? a0[6] : s0_w3;
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// Stage 1
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wire s1_w6 = sel1[7] ? a1[7] : a1[4];
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wire s1_w4 = sel1[6] ? a1[3] : s1_w6;
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wire s1_w5 = sel1[5] ? a1[5] : s1_w4;
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wire s1_w0 = sel1[0] ? a1[1] : x0;
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wire s1_w1 = sel1[1] ? a1[2] : s1_w0;
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wire s1_w2 = sel1[2] ? s1_w4 : s1_w1;
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wire s1_w3 = sel1[3] ? s1_w2 : s1_w5;
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assign x1 = sel1[4] ? a1[6] : s1_w3;
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// Stage 2
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wire s2_w6 = sel2[7] ? a2[7] : a2[4];
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wire s2_w4 = sel2[6] ? a2[3] : s2_w6;
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wire s2_w5 = sel2[5] ? a2[5] : s2_w4;
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wire s2_w0 = sel2[0] ? a2[1] : x1;
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wire s2_w1 = sel2[1] ? a2[2] : s2_w0;
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wire s2_w2 = sel2[2] ? s2_w4 : s2_w1;
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wire s2_w3 = sel2[3] ? s2_w2 : s2_w5;
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assign x = sel2[4] ? a2[6] : s2_w3;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce -allow-off-chain
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# Load design and run opt_clean and opt_reduce to remove unnecessary cells
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design -load postopt
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opt_clean
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opt_reduce
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# Check we got one pmux with correct number of inputs
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select -assert-count 0 t:$mux
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select -assert-count 1 t:$pmux
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design -reset
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log -pop
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