From ba709dc0ed01d3035450d6b0a7db726e8fca0ae6 Mon Sep 17 00:00:00 2001
From: williamzhu17 <williammzhu@gmail.com>
Date: Thu, 3 Apr 2025 10:37:32 -0700
Subject: [PATCH] added stress tests

---
 tests/silimate/extract_reduce_gates.ys | 116 +++++++++++++--
 tests/silimate/extract_reduce_muxes.ys | 188 ++++++++++++++++++++++---
 2 files changed, 268 insertions(+), 36 deletions(-)

diff --git a/tests/silimate/extract_reduce_gates.ys b/tests/silimate/extract_reduce_gates.ys
index c3a505651..c50db9bc7 100644
--- a/tests/silimate/extract_reduce_gates.ys
+++ b/tests/silimate/extract_reduce_gates.ys
@@ -824,29 +824,119 @@ log -pop
 
 
 
-# TODO
-log -header "Combinational feedback loop"
+log -header "Stress test"
 log -push
 design -reset
 read_verilog <<EOF
 module top (
-  input  wire a,
+  input  wire [7:0] a0,
+  input  wire [7:0] a1,
+  input  wire [7:0] a2,
   output wire y
 );
-  wire w0, w1;
+  wire c0, c1, c2;
 
-  // Two AND gates feeding each other
-  assign w0 = a & w1;
-  assign w1 = a & w0;
+  // Stage 0
+  wire s0_w0 = a0[0] & a0[1];
+  wire s0_w1 = a0[2] & a0[3];
+  wire s0_w2 = s0_w0 & s0_w1;
+  wire s0_w3 = s0_w2 & a0[4];
+  wire s0_w4 = a0[0] & a0[5];
+  wire s0_w5 = s0_w3 & a0[6];
+  wire s0_w6 = s0_w4 & a0[7];
+  assign c0 = s0_w5 & s0_w6;
 
-  assign y = w1;
+  // Stage 1
+  wire s1_w0 = a1[0] & a1[1];
+  wire s1_w1 = a1[2] & a1[3];
+  wire s1_w2 = s1_w0 & s1_w1;
+  wire s1_w3 = s1_w2 & a1[4];
+  wire s1_w4 = c0     & a1[5];
+  wire s1_w5 = s1_w3 & a1[6];
+  wire s1_w6 = s1_w4 & a1[7];
+  assign c1 = s1_w5 & s1_w6;
+
+  // Stage 2
+  wire s2_w0 = a2[0] & a2[1];
+  wire s2_w1 = a2[2] & a2[3];
+  wire s2_w2 = s2_w0 & s2_w1;
+  wire s2_w3 = s2_w2 & a2[4];
+  wire s2_w4 = c1     & a2[5];
+  wire s2_w5 = s2_w3 & a2[6];
+  wire s2_w6 = s2_w4 & a2[7];
+  assign c2 = s2_w5 & s2_w6;
+
+  assign y = c2;
 endmodule
 EOF
-# check -assert
+check -assert
 
 # Check equivalence after extract_reduce
-# equiv_opt -assert extract_reduce
-extract_reduce -allow-off-chain
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean to remove unnecessary wires
+design -load postopt
+extract_reduce
+opt_clean
+
+# Check final design has correct number of gates and inputs
+select -assert-count 0 t:$and
+select -assert-count 1 t:$reduce_and
+
+design -reset
+log -pop
+
+
+
+log -header "Stress test reconvergence"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input  wire [7:0] a0,
+  input  wire [7:0] a1,
+  input  wire [7:0] a2,
+  output wire y
+);
+  wire c0, c1, c2;
+
+  // Stage 0
+  wire s0_w0 = a0[0] & a0[1];
+  wire s0_w1 = a0[2] & a0[3];
+  wire s0_w2 = s0_w0 & s0_w1;
+  wire s0_w3 = s0_w2 & a0[4];
+  wire s0_w4 = s0_w2 & a0[5];
+  wire s0_w5 = s0_w3 & a0[6];
+  wire s0_w6 = s0_w4 & a0[7];
+  assign c0 = s0_w5 & s0_w6;
+
+  // Stage 1
+  wire s1_w0 = a1[0] & a1[1];
+  wire s1_w1 = a1[2] & a1[3];
+  wire s1_w2 = s1_w0 & s1_w1;
+  wire s1_w3 = s1_w2 & a1[4];
+  wire s1_w4 = s1_w2 & a1[5];
+  wire s1_w5 = s1_w3 & a1[6];
+  wire s1_w6 = s1_w4 & c0;
+  assign c1 = s1_w5 & s1_w6;
+
+  // Stage 2
+  wire s2_w0 = a2[0] & a2[1];
+  wire s2_w1 = a2[2] & a2[3];
+  wire s2_w2 = s2_w0 & s2_w1;
+  wire s2_w3 = s2_w2 & a2[4];
+  wire s2_w4 = s2_w2 & a2[5];
+  wire s2_w5 = s2_w3 & a2[6];
+  wire s2_w6 = s2_w4 & c1;
+  assign c2 = s2_w5 & s2_w6;
+
+  assign y = c2;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
 
 # Load design and run opt_clean to remove unnecessary wires
 design -load postopt
@@ -854,9 +944,7 @@ opt_clean
 
 # Check final design has correct number of gates and inputs
 select -assert-count 0 t:$and
-select -assert-count 2 t:$reduce_and
-select -assert-count 1 t:$reduce_and r:A_WIDTH=4 %i
-select -assert-count 1 t:$reduce_and r:A_WIDTH=6 %i
+select -assert-count 4 t:$reduce_and
 
 design -reset
 log -pop
\ No newline at end of file
diff --git a/tests/silimate/extract_reduce_muxes.ys b/tests/silimate/extract_reduce_muxes.ys
index b5cd3b2a1..4950f1a6b 100644
--- a/tests/silimate/extract_reduce_muxes.ys
+++ b/tests/silimate/extract_reduce_muxes.ys
@@ -394,47 +394,191 @@ log -pop
 
 
 
-# TODO check about infinite loop
-log -header "Mux with feedback that causes infinite loop"
+log -header "Stress test"
 log -push
 design -reset
 read_verilog <<EOF
 module top (
-  input wire [2:0] sel,
-  input wire [3:0] a,
+  input  wire [5:0] sel0,
+  input  wire [5:0] sel1,
+  input  wire [5:0] sel2,
+  input  wire [6:0] a0,
+  input  wire [6:0] a1,
+  input  wire [6:0] a2,
   output wire x
 );
-  wire w0, w1;
+  wire x0, x1;
 
-  assign w0 = sel[0] ? a[0] : w0;
-  assign w1 = sel[1] ? a[1] : w0;
-  assign x  = sel[2] ? a[2] : w1;
+  // Stage 0
+  wire s0_w0 = sel0[0] ? a0[1] : a0[0];
+  wire s0_w1 = sel0[1] ? a0[2] : s0_w0;
+  wire s0_w2 = sel0[2] ? a0[3] : s0_w1;
+  wire s0_w4 = sel0[5] ? a0[4] : a0[5];
+  wire s0_w3 = sel0[3] ? s0_w2 : s0_w4;
+  assign x0  = sel0[4] ? s0_w3 : a0[6];
+
+  // Stage 1
+  wire s1_w0 = sel1[0] ? a1[1] : a1[0];
+  wire s1_w1 = sel1[1] ? a1[2] : s1_w0;
+  wire s1_w2 = sel1[2] ? a1[3] : s1_w1;
+  wire s1_w4 = sel1[5] ? a1[4] : a1[5];
+  wire s1_w3 = sel1[3] ? s1_w2 : s1_w4;
+  assign x1  = sel1[4] ? s1_w3 : x0;
+
+  // Stage 2
+  wire s2_w0 = sel2[0] ? a2[1] : a2[0];
+  wire s2_w1 = sel2[1] ? a2[2] : s2_w0;
+  wire s2_w2 = sel2[2] ? a2[3] : s2_w1;
+  wire s2_w4 = sel2[5] ? a2[4] : a2[5];
+  wire s2_w3 = sel2[3] ? s2_w2 : s2_w4;
+  assign x   = sel2[4] ? s2_w3 : x1;
 endmodule
 EOF
-# check -assert
-
-autoname
-write_json dump_pre.json
-exec -- netlistsvg dump_pre.json -o dump_pre.svg
+check -assert
 
 # Check equivalence after extract_reduce
-# equiv_opt -assert extract_reduce
-extract_reduce -allow-off-chain
+equiv_opt -assert extract_reduce
 
 # Load design and run opt_clean and opt_reduce to remove unnecessary cells
-# design -load postopt
+design -load postopt
 opt_clean
 opt_reduce
 
-autoname
-write_json dump_post.json
-exec -- netlistsvg dump_post.json -o dump_post.svg
+# Check we got one pmux with correct number of inputs
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+
+design -reset
+log -pop
+
+
+
+log -header "Stress test with reconverging tree and no off chain"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input  wire [7:0] sel0,
+  input  wire [7:0] sel1,
+  input  wire [7:0] sel2,
+  input  wire [7:0] a0,
+  input  wire [7:0] a1,
+  input  wire [7:0] a2,
+  output wire x
+);
+  wire x0, x1;
+
+  // Stage 0
+  wire s0_w6 = sel0[7] ? a0[7] : a0[4];
+  wire s0_w4 = sel0[6] ? a0[3] : s0_w6;
+  wire s0_w5 = sel0[5] ? a0[5] : s0_w4;
+  wire s0_w0 = sel0[0] ? a0[1] : a0[0];
+  wire s0_w1 = sel0[1] ? a0[2] : s0_w0;
+  wire s0_w2 = sel0[2] ? s0_w4 : s0_w1;
+  wire s0_w3 = sel0[3] ? s0_w2 : s0_w5;
+  assign x0  = sel0[4] ? a0[6] : s0_w3;
+
+  // Stage 1
+  wire s1_w6 = sel1[7] ? a1[7] : a1[4];
+  wire s1_w4 = sel1[6] ? a1[3] : s1_w6;
+  wire s1_w5 = sel1[5] ? a1[5] : s1_w4;
+  wire s1_w0 = sel1[0] ? a1[1] : x0;
+  wire s1_w1 = sel1[1] ? a1[2] : s1_w0;
+  wire s1_w2 = sel1[2] ? s1_w4 : s1_w1;
+  wire s1_w3 = sel1[3] ? s1_w2 : s1_w5;
+  assign x1  = sel1[4] ? a1[6] : s1_w3;
+
+  // Stage 2
+  wire s2_w6 = sel2[7] ? a2[7] : a2[4];
+  wire s2_w4 = sel2[6] ? a2[3] : s2_w6;
+  wire s2_w5 = sel2[5] ? a2[5] : s2_w4;
+  wire s2_w0 = sel2[0] ? a2[1] : x1;
+  wire s2_w1 = sel2[1] ? a2[2] : s2_w0;
+  wire s2_w2 = sel2[2] ? s2_w4 : s2_w1;
+  wire s2_w3 = sel2[3] ? s2_w2 : s2_w5;
+  assign x   = sel2[4] ? a2[6] : s2_w3;
+endmodule
+
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce
+
+# Load design and run opt_clean and opt_reduce to remove unnecessary cells
+design -load postopt
+opt_clean
+opt_reduce
 
 # Check we got one pmux with correct number of inputs
 select -assert-count 0 t:$mux
-select -assert-count 2 t:$pmux
-select -assert-count 1 t:$pmux r:S_WIDTH=3 %i
-select -assert-count 1 t:$pmux r:S_WIDTH=6 %i
+select -assert-count 4 t:$pmux
+
+design -reset
+log -pop
+
+
+
+log -header "Stress test with reconverging tree and yes off chain"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input  wire [7:0] sel0,
+  input  wire [7:0] sel1,
+  input  wire [7:0] sel2,
+  input  wire [7:0] a0,
+  input  wire [7:0] a1,
+  input  wire [7:0] a2,
+  output wire x
+);
+  wire x0, x1;
+
+  // Stage 0
+  wire s0_w6 = sel0[7] ? a0[7] : a0[4];
+  wire s0_w4 = sel0[6] ? a0[3] : s0_w6;
+  wire s0_w5 = sel0[5] ? a0[5] : s0_w4;
+  wire s0_w0 = sel0[0] ? a0[1] : a0[0];
+  wire s0_w1 = sel0[1] ? a0[2] : s0_w0;
+  wire s0_w2 = sel0[2] ? s0_w4 : s0_w1;
+  wire s0_w3 = sel0[3] ? s0_w2 : s0_w5;
+  assign x0  = sel0[4] ? a0[6] : s0_w3;
+
+  // Stage 1
+  wire s1_w6 = sel1[7] ? a1[7] : a1[4];
+  wire s1_w4 = sel1[6] ? a1[3] : s1_w6;
+  wire s1_w5 = sel1[5] ? a1[5] : s1_w4;
+  wire s1_w0 = sel1[0] ? a1[1] : x0;
+  wire s1_w1 = sel1[1] ? a1[2] : s1_w0;
+  wire s1_w2 = sel1[2] ? s1_w4 : s1_w1;
+  wire s1_w3 = sel1[3] ? s1_w2 : s1_w5;
+  assign x1  = sel1[4] ? a1[6] : s1_w3;
+
+  // Stage 2
+  wire s2_w6 = sel2[7] ? a2[7] : a2[4];
+  wire s2_w4 = sel2[6] ? a2[3] : s2_w6;
+  wire s2_w5 = sel2[5] ? a2[5] : s2_w4;
+  wire s2_w0 = sel2[0] ? a2[1] : x1;
+  wire s2_w1 = sel2[1] ? a2[2] : s2_w0;
+  wire s2_w2 = sel2[2] ? s2_w4 : s2_w1;
+  wire s2_w3 = sel2[3] ? s2_w2 : s2_w5;
+  assign x   = sel2[4] ? a2[6] : s2_w3;
+endmodule
+
+EOF
+check -assert
+
+# Check equivalence after extract_reduce
+equiv_opt -assert extract_reduce -allow-off-chain
+
+# Load design and run opt_clean and opt_reduce to remove unnecessary cells
+design -load postopt
+opt_clean
+opt_reduce
+
+# Check we got one pmux with correct number of inputs
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
 
 design -reset
 log -pop
\ No newline at end of file