mirror of https://github.com/YosysHQ/yosys.git
modshr onehot pass
This commit is contained in:
Akash Levy
parent
242d87079a
commit
b4e94d9f13
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@ -34,6 +34,7 @@ PEEPOPT_PATTERN += passes/opt/peepopt_shiftmul_left.pmg
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PEEPOPT_PATTERN += passes/opt/peepopt_shiftadd.pmg
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PEEPOPT_PATTERN += passes/opt/peepopt_muldiv.pmg
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PEEPOPT_PATTERN += passes/opt/peepopt_muldiv_c.pmg
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PEEPOPT_PATTERN += passes/opt/peepopt_modshr_onehot.pmg
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PEEPOPT_PATTERN += passes/opt/peepopt_addsub_c.pmg
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PEEPOPT_PATTERN += passes/opt/peepopt_muxorder.pmg
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PEEPOPT_PATTERN += passes/opt/peepopt_formal_clockgateff.pmg
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@ -57,6 +57,9 @@ struct PeepoptPass : public Pass {
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log("\n");
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log(" * muldiv_c - Replace (A*B)/C with A*(B/C) when C is a const divisible by B.\n");
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log("\n");
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log(" * modshr_onehot - Replace a%%(mbase>>shiftamt) with a&((mbase-1)>>shiftamt)\n");
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log(" when mbase is a constant one-hot signal.\n");
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log("\n");
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log(" * shiftmul - Replace A>>(B*C) with A'>>(B<<K) where C and K are constants\n");
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log(" and A' is derived from A by appropriately inserting padding\n");
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log(" into the signal. (right variant)\n");
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@ -124,13 +127,14 @@ struct PeepoptPass : public Pass {
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if (formalclk) {
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pm.run_formal_clockgateff();
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} else {
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pm.run_shiftadd();
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pm.run_shiftmul_right();
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pm.run_shiftmul_left();
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pm.run_muldiv();
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pm.run_muldiv_c();
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pm.run_addsub_c();
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pm.run_sub_neg();
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pm.run_shiftadd();
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pm.run_shiftmul_right();
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pm.run_shiftmul_left();
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pm.run_muldiv();
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pm.run_muldiv_c();
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pm.run_modshr_onehot();
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pm.run_addsub_c();
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pm.run_sub_neg();
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if (muxorder)
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pm.run_muxorder();
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}
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@ -0,0 +1,123 @@
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pattern modshr_onehot
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//
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// Authored by Akash Levy of Silimate, Inc. under ISC license.
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//
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// Rewrite unsigned modulo by a right-shifted constant one-hot into a
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// bitwise mask:
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//
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// y = a % (mbase >> shiftamt) ===> y = a & ((mbase - 1) >> shiftamt)
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//
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// where `mbase` is a fully-constant one-hot signal. This eliminates a
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// variable divider, replacing it with a single constant-A right shift
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// and a bitwise AND.
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//
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// Correctness:
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// Because `mbase = 1 << B` for some constant bit index B,
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// `mbase >> shiftamt` is always either a power of two or zero.
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// For unsigned operands, `a % 2^k = a & (2^k - 1)`, and
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// `(mbase - 1) >> shiftamt` is exactly the lower-k-bits mask.
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// When `shiftamt > B` the original `a % 0` is undefined (Yosys
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// `const_mod` returns Sx); the rewrite yields `a & 0 = 0`, which is
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// a legal refinement of Sx.
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//
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// We match $mod first and then look for a $shr/$shiftx whose Y's
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// lower bits drive mod->B. This is critical because Verilog often
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// infers the shifter as 32 bits wide (signed integer parameters) and
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// only the lower bits actually feed the modulo.
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//
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state <SigSpec> mod_b
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state <int> mod_b_width
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state <Const> mbase_const
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state <int> onehot_pos
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match mod
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select mod->type.in($mod, $modfloor)
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// Signed modulo has different semantics for negative dividends;
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// the bitmask identity holds only for unsigned a.
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filter !param(mod, \A_SIGNED).as_bool()
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endmatch
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code mod_b mod_b_width
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mod_b = port(mod, \B);
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mod_b_width = GetSize(mod_b);
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endcode
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match shift
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// $shr / $shiftx perform logical operations regardless of A_SIGNED,
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// so we accept any A_SIGNED. $sshr is excluded because with
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// A_SIGNED=1 and a one-hot at the MSB it would sign-extend with
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// 1s, breaking the power-of-two assumption.
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select shift->type.in($shr, $shiftx)
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// B_SIGNED must be false so shiftamt is non-negative; for $shiftx
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// in particular a negative B would shift left, invalidating the
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// rewrite.
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filter !param(shift, \B_SIGNED).as_bool()
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// A must be a constant one-hot signal.
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filter port(shift, \A).is_fully_const()
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filter port(shift, \A).is_onehot()
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// shift->Y must be at least as wide as mod->B (we look at its low
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// bits only), and the lower `mod_b_width` bits of Y must exactly
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// equal mod->B. The shifter output is allowed to fan out to many
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// $mod cells (each one is rewritten independently); we do not
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// constrain nusers here.
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filter GetSize(port(shift, \Y)) >= mod_b_width
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filter port(shift, \Y).extract(0, mod_b_width) == mod_b
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endmatch
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code mbase_const onehot_pos
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mbase_const = port(shift, \A).as_const();
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mbase_const.is_onehot(&onehot_pos);
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endcode
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code
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{
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// If mod sees B as signed, the divisor bit pattern must encode a
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// non-negative value; reject when the one-hot bit sits at the MSB
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// of mbase (which would make it negative).
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if (param(mod, \B_SIGNED).as_bool() && onehot_pos == GetSize(mbase_const) - 1)
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reject;
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// Build mask_const = mbase - 1: bits [onehot_pos-1:0] = 1, rest = 0.
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Const mask_const(State::S0, GetSize(mbase_const));
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for (int i = 0; i < onehot_pos; i++)
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mask_const.set(i, State::S1);
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// `cell` is read by NEW_ID2_SUFFIX (kernel/yosys_common.h:321);
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// use the soon-to-be-converted $mod as the naming parent so the
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// new mask wire and shifter inherit a stable, debuggable name.
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Cell *cell = mod;
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// New shifter producing shifted_mask = mask_const >> shiftamt,
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// of the same type as the original shift but width-trimmed to
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// match mod->B.
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Wire *shifted_mask = module->addWire(NEW_ID2_SUFFIX("mask"), mod_b_width);
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Cell *new_shift = module->addCell(NEW_ID2_SUFFIX("maskshift"), shift->type);
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new_shift->setPort(\A, mask_const);
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new_shift->setPort(\B, port(shift, \B));
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new_shift->setPort(\Y, shifted_mask);
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new_shift->setParam(\A_SIGNED, false);
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new_shift->setParam(\B_SIGNED, false);
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new_shift->fixup_parameters();
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new_shift->set_src_attribute(mod->get_src_attribute());
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// Convert $mod -> $and in place: keep A and Y, retarget B to the
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// new shifted_mask wire, and refresh widths.
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mod->type = $and;
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mod->setPort(\B, shifted_mask);
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mod->setParam(\B_SIGNED, false);
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mod->fixup_parameters();
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module->rename(mod, NEW_ID2_SUFFIX("modmask"));
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// Do NOT autoremove(shift): a single shifter often fans out to
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// many $mod cells (e.g. inside a generate loop), and autoremove
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// blacklists the cell, preventing further matches for siblings.
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// Leave shift in place -- opt_clean will prune it later if all
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// of its Y bits have become dead.
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log("modshr_onehot pattern in %s: shift=%s, mod=%s\n",
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log_id(module), log_id(shift), log_id(mod));
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did_something = true;
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accept;
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}
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endcode
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@ -0,0 +1,338 @@
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log -header "Positive: mbase MSB one-hot (8'b1000_0000), shiftamt 3 bits"
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log -push
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design -reset
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read_verilog <<EOT
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module top(
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input [11:0] a,
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input [2:0] shiftamt,
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output [11:0] y
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);
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localparam [7:0] MBASE = 8'b1000_0000;
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assign y = a % (MBASE >> shiftamt);
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endmodule
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EOT
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check -assert
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equiv_opt -assert peepopt
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design -load postopt
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opt_clean
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select -assert-count 0 t:$mod
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select -assert-count 1 t:$and
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select -assert-count 1 t:$shr
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design -reset
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log -pop
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log -header "Positive: mbase non-MSB one-hot (8'b0010_0000)"
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log -push
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design -reset
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read_verilog <<EOT
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module top(
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input [11:0] a,
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input [1:0] shiftamt,
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output [11:0] y
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);
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localparam [7:0] MBASE = 8'b0010_0000;
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assign y = a % (MBASE >> shiftamt);
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endmodule
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EOT
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check -assert
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equiv_opt -assert peepopt
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design -load postopt
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opt_clean
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select -assert-count 0 t:$mod
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select -assert-count 1 t:$and
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select -assert-count 1 t:$shr
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design -reset
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log -pop
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log -header "Positive: shiftamt clog2(N) bits, divisor never zero (mbase = 1<<(N-1))"
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log -push
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design -reset
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read_verilog <<EOT
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module top(
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input [15:0] a,
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input [3:0] shiftamt,
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output [15:0] y
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);
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localparam [15:0] MBASE = 16'h8000;
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assign y = a % (MBASE >> shiftamt);
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endmodule
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EOT
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check -assert
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equiv_opt -assert peepopt
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design -load postopt
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opt_clean
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select -assert-count 0 t:$mod
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select -assert-count 1 t:$and
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select -assert-count 1 t:$shr
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design -reset
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log -pop
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log -header "Positive: low-position one-hot, shiftamt bounded so divisor != 0"
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log -push
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design -reset
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read_verilog <<EOT
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module top(
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input [7:0] a,
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input shiftamt,
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output [7:0] y
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);
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localparam [7:0] MBASE = 8'b0000_0010;
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assign y = a % (MBASE >> shiftamt);
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endmodule
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EOT
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check -assert
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equiv_opt -assert peepopt
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design -load postopt
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opt_clean
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select -assert-count 0 t:$mod
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select -assert-count 1 t:$and
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select -assert-count 1 t:$shr
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design -reset
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log -pop
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log -header "Positive: wider mbase than a, shiftamt sized so divisor != 0"
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log -push
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design -reset
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read_verilog <<EOT
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module top(
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input [3:0] a,
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input [1:0] shiftamt,
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output [3:0] y
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);
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localparam [7:0] MBASE = 8'b0001_0000;
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assign y = a % (MBASE >> shiftamt);
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endmodule
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EOT
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check -assert
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equiv_opt -assert peepopt
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design -load postopt
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opt_clean
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select -assert-count 0 t:$mod
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select -assert-count 1 t:$and
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select -assert-count 1 t:$shr
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design -reset
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log -pop
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log -header "Positive: \$shr A_SIGNED=1 (signed parameter), Y wider than mod->B"
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log -push
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design -reset
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read_verilog -sv <<EOT
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module top(
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input [11:0] a,
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input [1:0] shiftamt,
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output [11:0] y
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);
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// FIFO_DEPTH is inferred as a signed integer parameter, so the
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// synthesized \$shr cell ends up with A_SIGNED=1 even though the
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// value is positive. Verilog also widens the shifter Y to 32 bits;
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// only the low bits feed the modulo. shiftamt range 0..3 keeps
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// (FIFO_DEPTH >> shiftamt) in {32,16,8,4} -- never zero.
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parameter FIFO_DEPTH = 32;
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wire [5:0] divisor = FIFO_DEPTH >> shiftamt;
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assign y = a % divisor;
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endmodule
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EOT
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check -assert
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equiv_opt -assert peepopt
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design -load postopt
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opt_clean
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select -assert-count 0 t:$mod
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select -assert-count 1 t:$and
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select -assert-count 1 t:$shr
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design -reset
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log -pop
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log -header "Positive: shared shifter Y fans out to many \$mod cells (generate loop)"
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log -push
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design -reset
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read_verilog -sv <<EOT
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module top(
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input [11:0] a0, a1, a2, a3,
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input [1:0] shiftamt,
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output [11:0] y0, y1, y2, y3
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);
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parameter FIFO_DEPTH = 32;
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wire [5:0] divisor = FIFO_DEPTH >> shiftamt;
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assign y0 = a0 % divisor;
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assign y1 = a1 % divisor;
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assign y2 = a2 % divisor;
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assign y3 = a3 % divisor;
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endmodule
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EOT
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check -assert
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equiv_opt -assert peepopt
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design -load postopt
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opt_clean
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select -assert-count 0 t:$mod
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select -assert-count 4 t:$and
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# 4 mask shifters + 1 original (still drives the shared divisor wire
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# whose remaining bits may be dead). opt_clean keeps the original
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# while any of its Y bits has a name attached; check >= 4 shifters.
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select -assert-min 4 t:$shr
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design -reset
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log -pop
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log -header "Positive: rewrite still applied even when divisor can be 0; assert via peepopt only"
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log -push
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design -reset
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read_verilog <<EOT
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module top(
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input [7:0] a,
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input [2:0] shiftamt,
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output [7:0] y
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);
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localparam [7:0] MBASE = 8'b0000_0001;
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assign y = a % (MBASE >> shiftamt);
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endmodule
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EOT
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check -assert
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peepopt
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opt_clean
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select -assert-count 0 t:$mod
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select -assert-count 1 t:$and
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select -assert-count 1 t:$shr
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design -reset
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log -pop
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log -header "Negative: mbase is NOT one-hot (8'b0011_0000)"
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log -push
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design -reset
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read_verilog <<EOT
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module top(
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input [11:0] a,
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input [2:0] shiftamt,
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output [11:0] y
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);
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localparam [7:0] MBASE = 8'b0011_0000;
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assign y = a % (MBASE >> shiftamt);
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endmodule
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EOT
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check -assert
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-count 1 t:$mod
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select -assert-count 0 t:$and
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design -reset
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log -pop
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log -header "Negative: mbase is a wire (not constant) -- pattern must not match"
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log -push
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design -reset
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read_verilog <<EOT
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module top(
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input [11:0] a,
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input [7:0] mbase,
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input [2:0] shiftamt,
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output [11:0] y
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);
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assign y = a % (mbase >> shiftamt);
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endmodule
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EOT
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check -assert
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-count 1 t:$mod
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design -reset
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log -pop
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log -header "Negative: signed dividend (A_SIGNED=1 on $mod)"
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log -push
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design -reset
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read_verilog <<EOT
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module top(
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input signed [11:0] a,
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input [2:0] shiftamt,
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output signed [11:0] y
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);
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localparam signed [7:0] MBASE = 8'b0010_0000;
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assign y = a % $signed(MBASE >> shiftamt);
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endmodule
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EOT
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check -assert
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-count 1 t:$mod
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design -reset
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log -pop
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log -header "Negative: shifter is $shl (left shift) -- not the right pattern"
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log -push
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design -reset
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read_verilog <<EOT
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module top(
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input [11:0] a,
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input [2:0] shiftamt,
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output [11:0] y
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);
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localparam [7:0] MBASE = 8'b0000_0001;
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assign y = a % (MBASE << shiftamt);
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endmodule
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EOT
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check -assert
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-count 1 t:$mod
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design -reset
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log -pop
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log -header "Positive: shifter Y also drives an external probe (extra fanout OK)"
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log -push
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design -reset
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read_verilog <<EOT
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module top(
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input [11:0] a,
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input [1:0] shiftamt,
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output [11:0] y,
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output [7:0] probe
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||||
);
|
||||
localparam [7:0] MBASE = 8'b0010_0000;
|
||||
wire [7:0] divisor = MBASE >> shiftamt;
|
||||
assign y = a % divisor;
|
||||
assign probe = divisor;
|
||||
endmodule
|
||||
EOT
|
||||
check -assert
|
||||
equiv_opt -assert peepopt
|
||||
design -load postopt
|
||||
opt_clean
|
||||
# The original $shr must be preserved because it drives \probe; the
|
||||
# rewrite only retargets the $mod, replacing it with $and + a new mask
|
||||
# shifter.
|
||||
select -assert-count 0 t:$mod
|
||||
select -assert-count 1 t:$and
|
||||
select -assert-count 2 t:$shr
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
log -header "Negative: B_SIGNED=1 on $mod with one-hot at MSB of mbase"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOT
|
||||
module top(
|
||||
input [11:0] a,
|
||||
input [2:0] shiftamt,
|
||||
output [11:0] y
|
||||
);
|
||||
wire signed [7:0] divisor = $signed(8'b1000_0000) >>> shiftamt;
|
||||
assign y = a % divisor;
|
||||
endmodule
|
||||
EOT
|
||||
check -assert
|
||||
equiv_opt -assert peepopt
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$mod
|
||||
design -reset
|
||||
log -pop
|
||||
Loading…
Reference in New Issue