signorm: disable passes that use rewrite_sigspecs

passes/cmds/splitnets.cc

@@ -145,6 +145,9 @@ struct SplitnetsPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
+		// TODO disable signorm due to rewrite_sigspecs assert
+		design->sigNormalize(false);
+
 		// module_ports_db[module_name][old_port_name] = new_port_name_list
 		dict<IdString, dict<IdString, vector<IdString>>> module_ports_db;
 

passes/equiv/equiv_miter.cc

@@ -319,6 +319,9 @@ struct EquivMiterPass : public Pass {
 		worker.miter_name = RTLIL::escape_id(args[argidx++]);
 		extra_args(args, argidx, design);
 
+		// TODO disable signorm due to rewrite_sigspecs assert
+		design->sigNormalize(false);
+
 		if (design->module(worker.miter_name))
 			log_cmd_error("Miter module %s already exists.\n", worker.miter_name.unescape());
 

passes/sat/freduce.cc

@@ -827,6 +827,8 @@ struct FreducePass : public Pass {
 			break;
 		}
 		extra_args(args, argidx, design);
+		// TODO disable signorm due to rewrite_sigspecs assert
+		design->sigNormalize(false);
 
 		int bitcount = 0;
 		for (auto module : design->selected_modules()) {

passes/techmap/abc9_ops.cc

@@ -1446,6 +1446,7 @@ struct Abc9OpsPass : public Pass {
 		extra_args(args, argidx, design);
 
 		// TODO Disabled signorm because swap_names breaks fanout logic
+		// TODO disable signorm due to rewrite_sigspecs assert
 		design->sigNormalize(false);
 
 		if (!valid)

passes/techmap/constmap.cc

@@ -74,6 +74,9 @@ struct ConstmapPass : public Pass {
 		if (celltype.empty())
 			log_cmd_error("Missing required option -cell.\n");
 
+		// TODO disable signorm due to rewrite_sigspecs assert
+		design->sigNormalize(false);
+
 		if (design->has(celltype)) {
 			Module *existing = design->module(celltype);
 			bool has_port = false;

passes/techmap/hilomap.cc

@@ -105,6 +105,9 @@ struct HilomapPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
+		// TODO disable signorm due to rewrite_sigspecs assert
+		design->sigNormalize(false);
+
 		for (auto mod : design->selected_modules())
 		{
 			module = mod;