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rtlil: Speeds up Yosys by 17%

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This PR speeds up by roughly 17% across a wide spectrum of designs
tested at Google. Particularly for the mux generation pass.

Co-authored-by: Rasmus Larsen <[email protected]>
Signed-off-by: Ethan Mahintorabi <[email protected]>
This commit is contained in:
Ethan Mahintorabi
2023-09-21 10:46:11 +01:00
committed by Catherine
co-authored by Rasmus Larsen
parent c4762d930e
commit aa06809d64
1 changed files with 9 additions and 5 deletions
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kernel/rtlil.cc
+9 -5
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@@ -4031,16 +4031,20 @@ void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec
unpack();
other->unpack();
dict<RTLIL::SigBit, int> pattern_to_with;
for (int i = 0; i < GetSize(pattern.bits_); i++) {
if (pattern.bits_[i].wire != NULL) {
for (int j = 0; j < GetSize(bits_); j++) {
if (bits_[j] == pattern.bits_[i]) {
other->bits_[j] = with.bits_[i];
}
}
pattern_to_with.emplace(pattern.bits_[i], i);
}
}
for (int j = 0; j < GetSize(bits_); j++) {
auto it = pattern_to_with.find(bits_[j]);
if (it != pattern_to_with.end()) {
other->bits_[j] = with.bits_[it->second];
}
}
other->check();
}