tests: Tidy up bug3515

Add base case where mapping is possible for sanity checking.

tests/various/bug3515.ys

@@ -1,21 +1,31 @@
+# base case is able to map
 read_verilog << EOF
-module mod_and_or (
+module and_x3 (
-    input a,
+    input a, b, c, d,
-    input b,
-    input c,
-    input d,
     output reg y
 );
 
-always @(a,b,c,d) begin
+assign y = (a&b)&(c&d);
-    y <= (a&b)|(c&d);
+endmodule
-end
+EOF
+hierarchy -top and_x3
+opt
+extract -map ./bug3515.v
+select -assert-count 1 t:mod_74x08_3
+
+# more needles than haystacks; not able to map
+design -reset
+read_verilog << EOF
+module mod_and_or (
+    input a, b, c, d,
+    output reg y
+);
+
+assign y = (a&b)|(c&d);
 endmodule
 EOF
 hierarchy -top mod_and_or
-proc
 opt
-techmap -map ./bug3515.v
+extract -map ./bug3515.v
-proc
+select -assert-count 2 t:$and
-extract -map ./bug3515.v -verbose
+
-proc