From a8e8746fc0f0ce32e8d08ccd9886911a0288ed97 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 25 Nov 2025 07:35:19 +1300
Subject: [PATCH] tests: Tidy up bug3515

Add base case where mapping is possible for sanity checking.
---
 tests/various/bug3515.ys | 36 +++++++++++++++++++++++-------------
 1 file changed, 23 insertions(+), 13 deletions(-)

diff --git a/tests/various/bug3515.ys b/tests/various/bug3515.ys
index 63c2ccde2..783a75bb4 100644
--- a/tests/various/bug3515.ys
+++ b/tests/various/bug3515.ys
@@ -1,21 +1,31 @@
+# base case is able to map
 read_verilog << EOF
-module mod_and_or (
-    input a,
-    input b,
-    input c,
-    input d,
+module and_x3 (
+    input a, b, c, d,
     output reg y
 );
 
-always @(a,b,c,d) begin
-    y <= (a&b)|(c&d);
-end
+assign y = (a&b)&(c&d);
+endmodule
+EOF
+hierarchy -top and_x3
+opt
+extract -map ./bug3515.v
+select -assert-count 1 t:mod_74x08_3
+
+# more needles than haystacks; not able to map
+design -reset
+read_verilog << EOF
+module mod_and_or (
+    input a, b, c, d,
+    output reg y
+);
+
+assign y = (a&b)|(c&d);
 endmodule
 EOF
 hierarchy -top mod_and_or
-proc
 opt
-techmap -map ./bug3515.v
-proc
-extract -map ./bug3515.v -verbose
-proc
+extract -map ./bug3515.v
+select -assert-count 2 t:$and
+