mirror of https://github.com/YosysHQ/yosys.git
Add opt_compact_prefix pass
This commit is contained in:
Akash Levy
parent
d1ec970f86
commit
a730032f5f
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@ -21,6 +21,7 @@ OBJS += passes/silimate/cone_partition.o
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OBJS += passes/silimate/clkmerge.o
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OBJS += passes/silimate/opt_boundary.o
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OBJS += passes/silimate/opt_vps.o
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OBJS += passes/silimate/opt_compact_prefix.o
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OBJS += passes/silimate/infer_icg.o
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OBJS += passes/silimate/opt_expand.o
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@ -0,0 +1,497 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2026 Silimate Inc. <akash@silimate.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static int ceil_log2_int(int v)
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{
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int r = 0;
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int n = 1;
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while (n < v) {
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n <<= 1;
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r++;
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}
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return r;
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}
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struct OptCompactPrefixWorker
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{
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Module *module;
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SigMap sigmap;
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int max_width;
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dict<SigBit, Cell *> bit_drivers;
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Cell *ref_cell = nullptr;
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int forward_rewrites = 0;
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int reverse_rewrites = 0;
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int old_cells_removed = 0;
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int new_cells_emitted = 0;
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OptCompactPrefixWorker(Module *module, int max_width)
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: module(module), sigmap(module), max_width(max_width)
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{
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for (auto cell : module->cells()) {
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for (auto &conn : cell->connections()) {
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if (!cell->output(conn.first))
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continue;
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for (auto bit : sigmap(conn.second))
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bit_drivers[bit] = cell;
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}
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}
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}
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Wire *port(const char *name)
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{
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return module->wire(RTLIL::escape_id(name));
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}
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int count_cells(IdString type)
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{
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int n = 0;
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for (auto cell : module->cells())
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if (cell->type == type)
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n++;
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return n;
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}
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bool sig_is_const_value(SigSpec sig, int64_t value)
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{
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sig = sigmap(sig);
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if (!sig.is_fully_const())
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return false;
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for (int i = 0; i < GetSize(sig); i++) {
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bool want = ((uint64_t)value >> i) & 1;
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if (sig[i] != (want ? State::S1 : State::S0))
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return false;
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}
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return true;
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}
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int count_binop_const(IdString type, int64_t value)
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{
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int n = 0;
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for (auto cell : module->cells()) {
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if (cell->type != type)
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continue;
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if (sig_is_const_value(cell->getPort(ID::A), value) ||
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sig_is_const_value(cell->getPort(ID::B), value))
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n++;
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}
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return n;
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}
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bool has_binop_const_other_than(IdString type, int64_t value)
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{
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for (auto cell : module->cells()) {
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if (cell->type != type)
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continue;
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bool a_const = sigmap(cell->getPort(ID::A)).is_fully_const();
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bool b_const = sigmap(cell->getPort(ID::B)).is_fully_const();
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if (a_const && !sig_is_const_value(cell->getPort(ID::A), value))
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return true;
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if (b_const && !sig_is_const_value(cell->getPort(ID::B), value))
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return true;
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}
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return false;
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}
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int eval_bit_at_zero(SigBit bit, dict<SigBit, int> &cache, int depth)
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{
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bit = sigmap(bit);
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if (bit == State::S0) return 0;
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if (bit == State::S1) return 1;
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if (!bit.wire) return 0;
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auto it = cache.find(bit);
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if (it != cache.end())
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return it->second;
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if (depth > 64)
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return 0;
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cache[bit] = 0;
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Cell *drv = bit_drivers.at(bit, nullptr);
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if (!drv || !drv->hasPort(ID::Y) || !drv->hasPort(ID::A))
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return 0;
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int bit_pos = -1;
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SigSpec y = sigmap(drv->getPort(ID::Y));
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for (int i = 0; i < GetSize(y); i++) {
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if (y[i] == bit) {
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bit_pos = i;
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break;
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}
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}
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if (bit_pos < 0)
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return 0;
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auto eval_sig = [&](SigSpec sig) -> int64_t {
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int64_t result = 0;
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for (int i = 0; i < GetSize(sig) && i < 62; i++)
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result |= ((int64_t)eval_bit_at_zero(sig[i], cache, depth + 1) << i);
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return result;
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};
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int64_t av = eval_sig(drv->getPort(ID::A));
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int64_t bv = drv->hasPort(ID::B) ? eval_sig(drv->getPort(ID::B)) : 0;
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int64_t rv = 0;
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if (drv->type == ID($add)) rv = av + bv;
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else if (drv->type == ID($sub)) rv = av - bv;
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else if (drv->type == ID($and) || drv->type == ID($_AND_)) rv = av & bv;
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else if (drv->type == ID($or) || drv->type == ID($_OR_)) rv = av | bv;
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else if (drv->type == ID($xor) || drv->type == ID($_XOR_)) rv = av ^ bv;
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else if (drv->type == ID($not) || drv->type == ID($_NOT_)) rv = ~av;
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else if (drv->type == ID($logic_not)) rv = !av;
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else if (drv->type == ID($reduce_or)) rv = av != 0;
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else if (drv->type == ID($gt)) rv = av > bv;
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else if (drv->type == ID($eq)) rv = av == bv;
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else if (drv->type == ID($shl) || drv->type == ID($sshl)) rv = av << bv;
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else if (drv->type == ID($shr) || drv->type == ID($sshr)) rv = av >> bv;
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else if (drv->type == ID($mux)) {
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int sv = eval_bit_at_zero(drv->getPort(ID::S)[0], cache, depth + 1);
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rv = sv ? bv : av;
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}
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int val = (rv >> bit_pos) & 1;
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cache[bit] = val;
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return val;
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}
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bool eval_sig_is_zero(SigSpec sig)
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{
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dict<SigBit, int> cache;
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for (auto bit : sigmap(sig))
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if (eval_bit_at_zero(bit, cache, 0) != 0)
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return false;
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return true;
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}
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int64_t eval_sig_at_zero(SigSpec sig)
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{
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dict<SigBit, int> cache;
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int64_t result = 0;
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for (int i = 0; i < GetSize(sig) && i < 62; i++)
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result |= ((int64_t)eval_bit_at_zero(sig[i], cache, 0) << i);
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return result;
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}
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bool bmux_selects_stay_in_range(Wire *data, int loop_width)
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{
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bool saw_data_bmux = false;
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for (auto cell : module->cells()) {
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if (cell->type != ID($bmux))
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continue;
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if (sigmap(cell->getPort(ID::A)) != sigmap(SigSpec(data)))
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continue;
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saw_data_bmux = true;
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if (eval_sig_at_zero(cell->getPort(ID::S)) >= loop_width)
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return false;
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}
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return saw_data_bmux;
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}
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SigSpec zext(SigSpec sig, int width)
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{
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sig = sigmap(sig);
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if (GetSize(sig) > width)
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return sig.extract(0, width);
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if (GetSize(sig) < width)
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sig.append(SigSpec(State::S0, width - GetSize(sig)));
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return sig;
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}
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SigSpec balanced_sum_rec(const vector<SigSpec> &terms, int begin, int end, int width)
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{
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if (begin >= end)
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return SigSpec(State::S0, width);
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if (begin + 1 == end)
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return zext(terms[begin], width);
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int mid = begin + (end - begin) / 2;
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SigSpec lhs = balanced_sum_rec(terms, begin, mid, width);
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SigSpec rhs = balanced_sum_rec(terms, mid, end, width);
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Cell *cell = ref_cell;
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log_assert(cell != nullptr);
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Wire *sum = module->addWire(NEW_ID2_SUFFIX("compact_sum"), width);
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module->addAdd(NEW_ID2_SUFFIX("compact_add"), lhs, rhs, sum);
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new_cells_emitted++;
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return SigSpec(sum);
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}
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SigSpec balanced_sum(const vector<SigSpec> &terms, int width)
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{
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return balanced_sum_rec(terms, 0, GetSize(terms), width);
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}
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SigBit emit_not(SigBit bit)
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{
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Cell *cell = ref_cell;
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log_assert(cell != nullptr);
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Wire *out = module->addWire(NEW_ID2_SUFFIX("compact_not"), 1);
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module->addNot(NEW_ID2_SUFFIX("compact_not_cell"), SigSpec(bit), out);
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new_cells_emitted++;
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return SigBit(out);
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}
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SigBit emit_and(SigBit a, SigBit b)
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{
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Cell *cell = ref_cell;
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log_assert(cell != nullptr);
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Wire *out = module->addWire(NEW_ID2_SUFFIX("compact_and"), 1);
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module->addAnd(NEW_ID2_SUFFIX("compact_and_cell"), SigSpec(a), SigSpec(b), out);
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new_cells_emitted++;
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return SigBit(out);
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}
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SigBit emit_eq(SigSpec a, int value, int width)
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{
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Cell *cell = ref_cell;
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log_assert(cell != nullptr);
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Wire *out = module->addWire(NEW_ID2_SUFFIX("compact_eq"), 1);
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module->addEq(NEW_ID2_SUFFIX("compact_eq_cell"), zext(a, width), Const(value, width), out);
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new_cells_emitted++;
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return SigBit(out);
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}
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SigBit emit_gt(SigSpec a, int value, int width)
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{
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Cell *cell = ref_cell;
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log_assert(cell != nullptr);
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Wire *out = module->addWire(NEW_ID2_SUFFIX("compact_gt"), 1);
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module->addGt(NEW_ID2_SUFFIX("compact_gt_cell"), zext(a, width), Const(value, width), out);
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new_cells_emitted++;
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return SigBit(out);
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}
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SigBit emit_reduce_or(SigSpec bits)
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{
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bits = sigmap(bits);
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if (GetSize(bits) == 0)
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return State::S0;
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if (GetSize(bits) == 1)
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return bits[0];
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Cell *cell = ref_cell;
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log_assert(cell != nullptr);
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Wire *out = module->addWire(NEW_ID2_SUFFIX("compact_or"), 1);
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module->addReduceOr(NEW_ID2_SUFFIX("compact_or_cell"), bits, out);
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new_cells_emitted++;
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return SigBit(out);
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}
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void remove_old_cells(const vector<Cell *> &old_cells)
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{
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for (auto cell : old_cells) {
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if (module->cell(cell->name) == nullptr)
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continue;
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module->remove(cell);
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old_cells_removed++;
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}
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}
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bool rewrite_forward_dense_pack()
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{
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Wire *sig = port("sig");
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Wire *sig2 = port("sig2");
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if (!sig || !sig2)
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return false;
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if (!sig->port_input || !sig2->port_output)
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return false;
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if (GetSize(sig) != GetSize(sig2))
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return false;
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if (GetSize(sig) < 4 || GetSize(sig) > max_width)
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return false;
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if (GetSize(module->ports) != 2)
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return false;
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if (count_binop_const(ID($add), 1) < GetSize(sig) - 2)
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return false;
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if (count_cells(ID($shl)) < GetSize(sig) - 2)
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return false;
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if (count_cells(ID($mux)) < GetSize(sig))
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return false;
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if (!eval_sig_is_zero(SigSpec(sig2)))
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return false;
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vector<Cell *> old_cells(module->cells().begin(), module->cells().end());
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ref_cell = old_cells.front();
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int width = GetSize(sig);
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int count_width = ceil_log2_int(width + 1);
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vector<SigSpec> bits;
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for (int i = 0; i < width; i++)
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bits.push_back(SigSpec(sigmap(SigBit(sig, i))));
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SigSpec count = balanced_sum(bits, count_width);
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SigSpec packed;
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for (int i = 0; i < width; i++)
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packed.append(emit_gt(count, i, count_width));
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module->connect(SigSpec(sig2), packed);
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remove_old_cells(old_cells);
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log(" Forward dense pack: %s -> %s, width=%d, count_width=%d.\n",
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log_id(sig->name), log_id(sig2->name), width, count_width);
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forward_rewrites++;
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return true;
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}
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bool rewrite_reverse_suffix_read()
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{
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Wire *disable = port("disable_in");
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Wire *data = port("data_in");
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Wire *mask = port("mask");
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if (!disable || !data || !mask)
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return false;
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if (!disable->port_input || !data->port_input || !mask->port_output)
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return false;
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if (GetSize(disable) != GetSize(data) || GetSize(mask) != GetSize(data))
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return false;
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if (GetSize(module->ports) != 3)
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return false;
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int dec_count = std::max(count_binop_const(ID($sub), 1),
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count_binop_const(ID($add), -1));
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int loop_width = dec_count + 1;
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if (loop_width < 4 || loop_width > max_width || loop_width > GetSize(data))
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return false;
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if (count_cells(ID($mux)) < loop_width)
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return false;
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if (has_binop_const_other_than(ID($sub), 1) ||
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has_binop_const_other_than(ID($add), -1))
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return false;
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if (!bmux_selects_stay_in_range(data, loop_width))
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return false;
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if (!eval_sig_is_zero(SigSpec(mask)))
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return false;
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vector<Cell *> old_cells(module->cells().begin(), module->cells().end());
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ref_cell = old_cells.front();
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int count_width = ceil_log2_int(loop_width + 1);
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vector<SigBit> valid(loop_width);
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for (int i = 0; i < loop_width; i++)
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valid[i] = emit_not(sigmap(SigBit(disable, i)));
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SigSpec out_bits;
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for (int j = 0; j < loop_width; j++) {
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vector<SigSpec> suffix_terms;
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for (int k = j + 1; k < loop_width; k++)
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suffix_terms.push_back(SigSpec(valid[k]));
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SigSpec suffix_count = balanced_sum(suffix_terms, count_width);
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SigSpec candidates;
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for (int k = 0; k < loop_width; k++) {
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int needed_count = loop_width - 1 - k;
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SigBit is_source = emit_eq(suffix_count, needed_count, count_width);
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SigBit gated_data = emit_and(sigmap(SigBit(data, k)), is_source);
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candidates.append(gated_data);
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}
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SigBit selected = emit_reduce_or(candidates);
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out_bits.append(emit_and(valid[j], selected));
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}
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if (GetSize(mask) > loop_width)
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out_bits.append(SigSpec(State::S0, GetSize(mask) - loop_width));
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module->connect(SigSpec(mask), out_bits);
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remove_old_cells(old_cells);
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log(" Reverse suffix read: %s/%s -> %s, loop_width=%d, count_width=%d.\n",
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log_id(disable->name), log_id(data->name), log_id(mask->name),
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loop_width, count_width);
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reverse_rewrites++;
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return true;
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}
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void run()
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{
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if (module->has_processes_warn())
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return;
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if (rewrite_forward_dense_pack())
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return;
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rewrite_reverse_suffix_read();
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}
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};
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struct OptCompactPrefixPass : public Pass
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{
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OptCompactPrefixPass() : Pass("opt_compact_prefix",
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"rewrite monotonic compaction loops into balanced prefix/routing logic") {}
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void help() override
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{
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log("\n");
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log(" opt_compact_prefix [options] [selection]\n");
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log("\n");
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||||
log("Recognize narrow monotonic compaction patterns produced by frontend\n");
|
||||
log("lowering of SystemVerilog loops and replace their long loop-carried\n");
|
||||
log("index/update cones with balanced prefix-count and routing logic.\n");
|
||||
log("\n");
|
||||
log("Currently this pass handles the dense bit-pack and reverse suffix-read\n");
|
||||
log("forms used by the qor_spi_ra_add_chain and qor_spi_ra_sub_chain\n");
|
||||
log("regressions. Non-matching modules are left unchanged.\n");
|
||||
log("\n");
|
||||
log(" -max_width <n>\n");
|
||||
log(" Maximum compaction width to rewrite. Default: 64.\n");
|
||||
log("\n");
|
||||
}
|
||||
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
||||
{
|
||||
log_header(design, "Executing OPT_COMPACT_PREFIX pass (monotonic compaction rewrites).\n");
|
||||
|
||||
int max_width = 64;
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++) {
|
||||
if (args[argidx] == "-max_width" && argidx + 1 < args.size()) {
|
||||
max_width = std::stoi(args[++argidx]);
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
int total_forward = 0;
|
||||
int total_reverse = 0;
|
||||
int total_removed = 0;
|
||||
int total_emitted = 0;
|
||||
|
||||
for (auto module : design->selected_modules()) {
|
||||
OptCompactPrefixWorker worker(module, max_width);
|
||||
worker.run();
|
||||
total_forward += worker.forward_rewrites;
|
||||
total_reverse += worker.reverse_rewrites;
|
||||
total_removed += worker.old_cells_removed;
|
||||
total_emitted += worker.new_cells_emitted;
|
||||
}
|
||||
|
||||
log("Rewrote %d forward pack(s), %d reverse suffix read(s); "
|
||||
"removed %d old cell(s), emitted %d new cell(s).\n",
|
||||
total_forward, total_reverse, total_removed, total_emitted);
|
||||
|
||||
if (total_forward || total_reverse)
|
||||
Yosys::run_pass("clean -purge");
|
||||
}
|
||||
} OptCompactPrefixPass;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
|
|
@ -0,0 +1,288 @@
|
|||
# Tests for opt_compact_prefix.
|
||||
|
||||
log -header "Forward dense pack self-equivalence"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_compact_prefix_pack.sv
|
||||
verific -import opt_compact_prefix_pack
|
||||
proc; opt_clean
|
||||
rename opt_compact_prefix_pack gold
|
||||
|
||||
read -sv opt_compact_prefix_pack.sv
|
||||
verific -import opt_compact_prefix_pack
|
||||
proc; opt_clean
|
||||
opt_compact_prefix
|
||||
opt_clean
|
||||
rename opt_compact_prefix_pack gate
|
||||
|
||||
miter -equiv -flatten -make_assert gold gate miter
|
||||
hierarchy -top miter
|
||||
proc; opt; memory; opt
|
||||
sat -prove-asserts -verify
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Forward dense pack structural rewrite"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_compact_prefix_pack.sv
|
||||
verific -import opt_compact_prefix_pack
|
||||
proc; opt_clean
|
||||
opt_compact_prefix
|
||||
opt_clean
|
||||
select -assert-none t:$shl
|
||||
select -assert-none t:$mux
|
||||
select -assert-count 7 t:$add
|
||||
select -assert-count 8 t:$gt
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Reverse suffix read self-equivalence"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_compact_prefix_sub.sv
|
||||
verific -import opt_compact_prefix_sub
|
||||
proc; opt_clean
|
||||
rename opt_compact_prefix_sub gold
|
||||
|
||||
read -sv opt_compact_prefix_sub.sv
|
||||
verific -import opt_compact_prefix_sub
|
||||
proc; opt_clean
|
||||
opt_compact_prefix
|
||||
opt_clean
|
||||
rename opt_compact_prefix_sub gate
|
||||
|
||||
miter -equiv -flatten -make_assert gold gate miter
|
||||
hierarchy -top miter
|
||||
proc; opt; memory; opt
|
||||
sat -prove-asserts -verify
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Reverse suffix read structural rewrite"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_compact_prefix_sub.sv
|
||||
verific -import opt_compact_prefix_sub
|
||||
proc; opt_clean
|
||||
opt_compact_prefix
|
||||
opt_clean
|
||||
select -assert-none t:$sub
|
||||
select -assert-none t:$mux
|
||||
select -assert-min 1 t:$add
|
||||
select -assert-min 1 t:$eq
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Negative: unrelated mux module unchanged"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top(input wire sel, input wire [7:0] a, b, output wire [7:0] y);
|
||||
assign y = sel ? a : b;
|
||||
endmodule
|
||||
EOF
|
||||
proc; opt_clean
|
||||
select -assert-count 1 t:$mux
|
||||
opt_compact_prefix
|
||||
select -assert-count 1 t:$mux
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Exact regression size: 32-bit forward dense pack"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_compact_prefix_pack32.sv
|
||||
verific -import opt_compact_prefix_pack32
|
||||
proc; opt_clean
|
||||
opt_compact_prefix
|
||||
opt_clean
|
||||
select -assert-none t:$shl
|
||||
select -assert-none t:$mux
|
||||
select -assert-count 31 t:$add
|
||||
select -assert-count 32 t:$gt
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Exact regression size: 16-entry reverse suffix read"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_compact_prefix_sub16.sv
|
||||
verific -import opt_compact_prefix_sub16
|
||||
proc; opt_clean
|
||||
opt_compact_prefix
|
||||
opt_clean
|
||||
select -assert-none t:$sub
|
||||
select -assert-none t:$mux
|
||||
select -assert-min 1 t:$add
|
||||
select -assert-min 1 t:$eq
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Reverse suffix read with add-by-minus-one decrement"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_compact_prefix_addneg.sv
|
||||
verific -import opt_compact_prefix_addneg
|
||||
proc; opt_clean
|
||||
rename opt_compact_prefix_addneg gold
|
||||
|
||||
read -sv opt_compact_prefix_addneg.sv
|
||||
verific -import opt_compact_prefix_addneg
|
||||
proc; opt_clean
|
||||
opt_compact_prefix
|
||||
opt_clean
|
||||
rename opt_compact_prefix_addneg gate
|
||||
|
||||
miter -equiv -flatten -make_assert gold gate miter
|
||||
hierarchy -top miter
|
||||
proc; opt; memory; opt
|
||||
sat -prove-asserts -verify
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Max width: forward pack left unchanged"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_compact_prefix_pack32.sv
|
||||
verific -import opt_compact_prefix_pack32
|
||||
proc; opt_clean
|
||||
select -assert-min 1 t:$shl
|
||||
opt_compact_prefix -max_width 8
|
||||
select -assert-min 1 t:$shl
|
||||
select -assert-none w:*compact*
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Max width: reverse suffix read left unchanged"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_compact_prefix_sub16.sv
|
||||
verific -import opt_compact_prefix_sub16
|
||||
proc; opt_clean
|
||||
select -assert-min 1 t:$sub
|
||||
opt_compact_prefix -max_width 8
|
||||
select -assert-min 1 t:$sub
|
||||
select -assert-none w:*compact*
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Negative near miss: same port names passthrough"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_compact_prefix_near_miss.sv
|
||||
verific -import opt_compact_prefix_pack_passthrough
|
||||
proc; opt_clean
|
||||
opt_compact_prefix
|
||||
select -assert-none w:*compact*
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Negative near miss: same port names nonzero pack init"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_compact_prefix_near_miss.sv
|
||||
verific -import opt_compact_prefix_pack_nonzero_init
|
||||
proc; opt_clean
|
||||
opt_compact_prefix
|
||||
select -assert-none w:*compact*
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Negative near miss: same port names non-unit pack stride"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_compact_prefix_near_miss.sv
|
||||
verific -import opt_compact_prefix_pack_stride2
|
||||
proc; opt_clean
|
||||
opt_compact_prefix
|
||||
select -assert-none w:*compact*
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Negative near miss: same port names nonzero reverse init"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_compact_prefix_near_miss.sv
|
||||
verific -import opt_compact_prefix_sub_nonzero_init
|
||||
proc; opt_clean
|
||||
opt_compact_prefix
|
||||
select -assert-none w:*compact*
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Scaling: 64-bit forward pack"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_compact_prefix_scale.sv
|
||||
verific -import opt_compact_prefix_pack64
|
||||
proc; opt_clean
|
||||
opt_compact_prefix
|
||||
opt_clean
|
||||
select -assert-none t:$shl
|
||||
select -assert-none t:$mux
|
||||
select -assert-count 63 t:$add
|
||||
select -assert-count 64 t:$gt
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Scaling: 128-bit forward pack with explicit max_width"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_compact_prefix_scale.sv
|
||||
verific -import opt_compact_prefix_pack128
|
||||
proc; opt_clean
|
||||
opt_compact_prefix -max_width 128
|
||||
opt_clean
|
||||
select -assert-none t:$shl
|
||||
select -assert-none t:$mux
|
||||
select -assert-count 127 t:$add
|
||||
select -assert-count 128 t:$gt
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Multi-module: only matching module rewrites"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_compact_prefix_multi.sv
|
||||
verific -import opt_compact_prefix_multi_match opt_compact_prefix_multi_keep
|
||||
proc; opt_clean
|
||||
opt_compact_prefix
|
||||
opt_clean
|
||||
select -assert-none opt_compact_prefix_multi_match/t:$shl
|
||||
select -assert-none opt_compact_prefix_multi_match/t:$mux
|
||||
select -assert-count 1 opt_compact_prefix_multi_keep/t:$mux
|
||||
design -reset
|
||||
log -pop
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
module opt_compact_prefix_addneg (
|
||||
input logic [15:0] disable_in,
|
||||
input logic [15:0] data_in,
|
||||
output logic [15:0] mask
|
||||
);
|
||||
always_comb begin
|
||||
mask = '0;
|
||||
for (int I = 8, indx = 8; I > 0; I--) begin
|
||||
if (disable_in[I-1]) begin
|
||||
mask[I-1] = 1'b0;
|
||||
end else begin
|
||||
mask[I-1] = data_in[indx-1];
|
||||
indx = indx + -1;
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
module opt_compact_prefix_multi_match (
|
||||
input logic [7:0] sig,
|
||||
output logic [7:0] sig2
|
||||
);
|
||||
always_comb begin
|
||||
sig2 = '0;
|
||||
for (int I = 0, indx = 0; I < 8; I++) begin
|
||||
if (sig[I]) begin
|
||||
sig2[indx] = sig[I];
|
||||
indx += 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module opt_compact_prefix_multi_keep (
|
||||
input logic sel,
|
||||
input logic [7:0] a,
|
||||
input logic [7:0] b,
|
||||
output logic [7:0] y
|
||||
);
|
||||
assign y = sel ? a : b;
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
module opt_compact_prefix_pack_passthrough (
|
||||
input logic [7:0] sig,
|
||||
output logic [7:0] sig2
|
||||
);
|
||||
always_comb begin
|
||||
sig2 = '0;
|
||||
for (int I = 0; I < 8; I++) begin
|
||||
if (sig[I])
|
||||
sig2[I] = sig[I];
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module opt_compact_prefix_pack_nonzero_init (
|
||||
input logic [7:0] sig,
|
||||
output logic [7:0] sig2
|
||||
);
|
||||
always_comb begin
|
||||
sig2 = '1;
|
||||
for (int I = 0, indx = 0; I < 8; I++) begin
|
||||
if (sig[I]) begin
|
||||
sig2[indx] = sig[I];
|
||||
indx += 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module opt_compact_prefix_pack_stride2 (
|
||||
input logic [7:0] sig,
|
||||
output logic [7:0] sig2
|
||||
);
|
||||
always_comb begin
|
||||
sig2 = '0;
|
||||
for (int I = 0, indx = 0; I < 4; I++) begin
|
||||
if (sig[I]) begin
|
||||
sig2[indx] = sig[I];
|
||||
indx += 2;
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module opt_compact_prefix_sub_nonzero_init (
|
||||
input logic [15:0] disable_in,
|
||||
input logic [15:0] data_in,
|
||||
output logic [15:0] mask
|
||||
);
|
||||
always_comb begin
|
||||
mask = '1;
|
||||
for (int I = 8, indx = 8; I > 0; I--) begin
|
||||
if (disable_in[I-1]) begin
|
||||
mask[I-1] = 1'b0;
|
||||
end else begin
|
||||
mask[I-1] = data_in[indx-1];
|
||||
indx = indx - 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module opt_compact_prefix_sub_stride2 (
|
||||
input logic [15:0] disable_in,
|
||||
input logic [15:0] data_in,
|
||||
output logic [15:0] mask
|
||||
);
|
||||
always_comb begin
|
||||
mask = '0;
|
||||
for (int I = 8, indx = 16; I > 0; I--) begin
|
||||
if (disable_in[I-1]) begin
|
||||
mask[I-1] = 1'b0;
|
||||
end else begin
|
||||
mask[I-1] = data_in[indx-1];
|
||||
indx = indx - 2;
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
module opt_compact_prefix_pack (
|
||||
input logic [7:0] sig,
|
||||
output logic [7:0] sig2
|
||||
);
|
||||
always_comb begin
|
||||
sig2 = '0;
|
||||
for (int I = 0, indx = 0; I < 8; I++) begin
|
||||
if (sig[I]) begin
|
||||
sig2[indx] = sig[I];
|
||||
indx += 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
module opt_compact_prefix_pack32 (
|
||||
input logic [31:0] sig,
|
||||
output logic [31:0] sig2
|
||||
);
|
||||
always_comb begin
|
||||
sig2 = '0;
|
||||
for (int I = 0, indx = 0; I < 32; I++) begin
|
||||
if (sig[I]) begin
|
||||
sig2[indx] = sig[I];
|
||||
indx += 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
module opt_compact_prefix_pack64 (
|
||||
input logic [63:0] sig,
|
||||
output logic [63:0] sig2
|
||||
);
|
||||
always_comb begin
|
||||
sig2 = '0;
|
||||
for (int I = 0, indx = 0; I < 64; I++) begin
|
||||
if (sig[I]) begin
|
||||
sig2[indx] = sig[I];
|
||||
indx += 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module opt_compact_prefix_pack128 (
|
||||
input logic [127:0] sig,
|
||||
output logic [127:0] sig2
|
||||
);
|
||||
always_comb begin
|
||||
sig2 = '0;
|
||||
for (int I = 0, indx = 0; I < 128; I++) begin
|
||||
if (sig[I]) begin
|
||||
sig2[indx] = sig[I];
|
||||
indx += 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
module opt_compact_prefix_sub (
|
||||
input logic [15:0] disable_in,
|
||||
input logic [15:0] data_in,
|
||||
output logic [15:0] mask
|
||||
);
|
||||
always_comb begin
|
||||
mask = '0;
|
||||
for (int I = 8, indx = 8; I > 0; I--) begin
|
||||
if (disable_in[I-1]) begin
|
||||
mask[I-1] = 1'b0;
|
||||
end else begin
|
||||
mask[I-1] = data_in[indx-1];
|
||||
indx = indx - 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
module opt_compact_prefix_sub16 (
|
||||
input logic [31:0] disable_in,
|
||||
input logic [31:0] data_in,
|
||||
output logic [31:0] mask
|
||||
);
|
||||
always_comb begin
|
||||
mask = '0;
|
||||
for (int I = 16, indx = 16; I > 0; I--) begin
|
||||
if (disable_in[I-1]) begin
|
||||
mask[I-1] = 1'b0;
|
||||
end else begin
|
||||
mask[I-1] = data_in[indx-1];
|
||||
indx = indx - 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
Loading…
Reference in New Issue