mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #174 from Silimate/feat/fst_reuse
[ENG-2072] Rename reg_rename pass argument from -vcd to -waveform
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commit
d1ec970f86
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@ -240,10 +240,11 @@ struct RegRenamePass : public Pass {
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log("\n");
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log(" reg_rename [options]\n");
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log("\n");
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log(" -vcd <filename>\n");
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log(" vcd file to extract original register width from\n");
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log(" -waveform <filename>\n");
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log(" waveform file (VCD or FST) to extract original register widths from.\n");
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log(" VCD inputs are converted via the external vcd2fst tool.\n");
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log(" -scope <scope>\n");
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log(" scope to process in vcd file\n");
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log(" scope to process in the waveform\n");
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log("\n");
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log(" -d\n");
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log(" enable debug output\n");
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@ -254,13 +255,13 @@ struct RegRenamePass : public Pass {
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log_header(design, "Executing reg_rename pass\n");
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// Argument parsing
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std::string vcd_filename;
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std::string waveform_filename;
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std::string scope;
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bool debug = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-vcd" && argidx + 1 < args.size()) {
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vcd_filename = args[++argidx];
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if (args[argidx] == "-waveform" && argidx + 1 < args.size()) {
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waveform_filename = args[++argidx];
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continue;
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}
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if (args[argidx] == "-scope" && argidx + 1 < args.size()) {
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@ -280,12 +281,12 @@ struct RegRenamePass : public Pass {
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if (!topmod)
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log_error("No top module found!\n");
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// Extract pre-optimization signal widths from VCD file
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// Extract pre-optimization signal widths from waveform file
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dict<std::string, RegInfo> vcd_reg_widths;
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if (!vcd_filename.empty()) {
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log("Reading VCD file: %s\n", vcd_filename.c_str());
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if (!waveform_filename.empty()) {
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log("Reading waveform file: %s\n", waveform_filename.c_str());
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try {
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FstData fst(vcd_filename);
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FstData fst(waveform_filename);
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if (scope.empty()) {
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scope = fst.autoScope(topmod);
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if (scope.empty()) {
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@ -295,7 +296,7 @@ struct RegRenamePass : public Pass {
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}
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log("Using scope: \"%s\"\n", scope.c_str());
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// Extract all signals from the VCD file (registers can be 'reg' or 'wire' in VCDs)
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// Extract all signals from the waveform (registers can be 'reg' or 'wire' in VCDs)
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for (auto &var : fst.getVars()) {
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std::string vcd_scope = var.scope;
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std::string signal_name = var.name;
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@ -327,7 +328,7 @@ struct RegRenamePass : public Pass {
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int width = var.width;
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int offset = std::min(msb, lsb);
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// Map the register's vcd scope and name to
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// Map the register's scope and name to
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// its original width and offset for later lookup.
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signal_name = RTLIL::unescape_id(signal_name);
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vcd_reg_widths[vcd_scope + "." + signal_name] = {width, offset};
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@ -336,13 +337,13 @@ struct RegRenamePass : public Pass {
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signal_name.c_str(), vcd_scope.c_str(),
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offset + width - 1, offset, width);
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}
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log("Extracted %d signal widths from VCD\n", GetSize(vcd_reg_widths));
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log("Extracted %d signal widths from waveform\n", GetSize(vcd_reg_widths));
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} catch (const std::exception &e) {
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log_error("Failed to read VCD file '%s': %s\n",
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vcd_filename.c_str(), e.what());
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log_error("Failed to read waveform file '%s': %s\n",
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waveform_filename.c_str(), e.what());
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}
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} else {
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log_error("No VCD file provided. Use -vcd option.\n");
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log_error("No waveform file provided. Use -waveform option.\n");
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}
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// STEP 2: Build hierarchy and process
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