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16 lines
365 B
Plaintext
16 lines
365 B
Plaintext
# https://github.com/YosysHQ/yosys/issues/6235
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# '&get' loses the mapping
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read_verilog <<EOT
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module top(input [7:0] a, b, input [2:0] s, output [7:0] y);
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assign y = (a << s) | (b >> s);
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endmodule
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EOT
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hierarchy -top top
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proc
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techmap
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opt
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logger -expect error "ABC returned unmapped node" 1
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abc_new -liberty openroad/cm_test_cells.lib -script +&put;strash;map;&get
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