Check $mul/$div signedness.

passes/opt/peepopt_muldiv_c.pmg

@@ -34,6 +34,7 @@ match div
 	// Check that b_const and c_const is constant
 	filter b_const.is_fully_const()
 	filter port(div, \B).is_fully_const()
+	filter param(div, \A_SIGNED).as_bool() == param(mul, \A_SIGNED).as_bool()
 	index <SigSpec> remove_bottom_padding(port(div, \A)) === mul_y
 endmatch
 

tests/various/peepopt.ys

@@ -365,3 +365,45 @@ end
 EOT
 
 equiv_opt -assert peepopt
+
+####################
+
+#6255
+design -reset
+read_verilog <<EOT
+module peepopt_muldiv_c_0(input signed [3:0] a, output [8:0] y);
+wire signed [8:0] p = a * 5'sd9;
+assign y = $unsigned(p) / 9'd3;
+endmodule
+EOT
+
+prep -nokeepdc
+equiv_opt -assert peepopt
+design -load postopt
+select -assert-count 1 t:$div
+
+design -reset
+read_verilog <<EOT
+module peepopt_muldiv_c_1(input [5:0] a, output [7:0] y);
+wire [7:0] p = a * 2'd3;
+assign y = $signed(p) / 3'sd3;
+endmodule
+EOT
+
+prep -nokeepdc
+equiv_opt -assert peepopt
+design -load postopt
+select -assert-count 1 t:$div
+
+design -reset
+read_verilog <<EOT
+module peepopt_muldiv_c_2(input signed [3:0] a, output signed [8:0] y);
+wire signed [8:0] p = a * 5'sd9;
+assign y = p / 9'sd3;
+endmodule
+EOT
+
+prep -nokeepdc
+equiv_opt -assert peepopt
+design -load postopt
+select -assert-count 0 t:$div