From 9e6d66d74e7ec1944be6f724d3fe28fd9ba14c62 Mon Sep 17 00:00:00 2001
From: Chia-Hsiang Chang <h511168@nehs.hc.edu.tw>
Date: Tue, 12 May 2026 00:01:29 -0700
Subject: [PATCH] chore: log error when no scope found

---
 passes/sat/sim.cc | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 7533023d4..be689d218 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -1612,7 +1612,11 @@ struct SimWorker : SimShared
 				for (auto wire : m->wires()) {
 					if (!wire->port_input) continue;
 					fstHandle id = fst->getHandle(iscope + "." + RTLIL::unescape_id(wire->name));
-					if (id != 0) t->fst_inputs[wire] = id;
+					if (id == 0) {
+						log_error("Can't find port '%s' on module '%s' in FST.\n",
+							(iscope + "." + RTLIL::unescape_id(wire->name)).c_str(), RTLIL::unescape_id(m->name).c_str());
+					}
+					t->fst_inputs[wire] = id;
 				}
 				t->addAdditionalInputs();
 			}