From 941be57cae16ad00824b26a56d1b75d77c0896a7 Mon Sep 17 00:00:00 2001
From: Advay Singh <144560982+AdvaySingh1@users.noreply.github.com>
Date: Tue, 3 Feb 2026 08:41:53 -0800
Subject: [PATCH] Added design->select after setting strpool_attribute for
 non-special case cells

Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com>
---
 passes/techmap/abc.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index de551ba5f..bdf901014 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -1753,7 +1753,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, dict<SigSpec, std::string> &
 			cell->setPort(conn.first, newsig);
 		}
 		cell->add_strpool_attribute(ID::src, src_pool); // SILIMATE: set src attribute from wire pool
-
+		design->select(module, cell);
 	}
 
 	for (auto conn : mapped_mod->connections()) {