mirror of
https://github.com/YosysHQ/yosys.git
synced 2026-10-06 10:03:36 +02:00
Initial new driver
This commit is contained in:
Miodrag Milanovic
@@ -420,6 +420,7 @@ endif()
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yosys_expand_components(library_components essentials ${YOSYS_COMPONENTS})
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if (NOT YOSYS_BUILD_PYTHON_ONLY)
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yosys_expand_components(driver_components driver ${YOSYS_COMPONENTS})
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yosys_expand_components(yc_components yc ${YOSYS_COMPONENTS})
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endif()
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# Main Yosys executable (compiler driver).
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@@ -443,6 +444,13 @@ if (NOT YOSYS_BUILD_PYTHON_ONLY)
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endif()
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target_compile_options(yosys PRIVATE -fsanitize=undefined)
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yosys_cxx_executable(yc
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OUTPUT_NAME yc
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INSTALL_IF ${YOSYS_INSTALL_DRIVER}
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)
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yosys_link_components(yc PRIVATE ${yc_components})
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target_compile_options(yc PRIVATE -fsanitize=undefined)
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endif()
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# Yosys components as a library.
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@@ -187,4 +187,18 @@ if (NOT YOSYS_BUILD_PYTHON_ONLY)
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essentials
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BOOTSTRAP
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)
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yosys_core(yc
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yc.cc
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REQUIRES
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essentials
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LIBRARIES
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fmt::fmt
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slang::slang
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$<${YOSYS_ENABLE_READLINE}:PkgConfig::readline>
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$<${YOSYS_ENABLE_EDITLINE}:PkgConfig::editline>
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$<${YOSYS_ENABLE_TCL}:PkgConfig::tcl>
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$<${YOSYS_ENABLE_PYTHON}:Python3::Python>
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BOOTSTRAP
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)
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endif()
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+741
@@ -0,0 +1,741 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <[email protected]>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "slang/util/CommandLine.h"
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#include <fmt/color.h>
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#include <fmt/format.h>
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YOSYS_NAMESPACE_BEGIN
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using namespace slang;
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bool is_verbose = false;
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bool show_build_status = false;
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class ColorLogSink : public LogSink
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{
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public:
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bool should_log(const LogMessage &msg) const override;
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void log(const LogMessage &msg) override;
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};
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bool ColorLogSink::should_log(const LogMessage &msg) const
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{
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if (is_verbose)
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return true;
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else
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return (msg.severity == LogSeverity::Warning || msg.severity == LogSeverity::Error);
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//return (msg.severity == LogSeverity::Warning || msg.severity == LogSeverity::Error || msg.severity == LogSeverity::Header);
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}
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//static constexpr std::array<std::string_view, 4> spinner = { "-", "\\", "|", "/" };
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//static int counter = 0;
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void ColorLogSink::log(const LogMessage &msg)
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{
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FILE *f = stderr;
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switch (msg.severity) {
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case LogSeverity::Warning:
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fmt::print(f, fg(fmt::terminal_color::bright_yellow), "{}", msg.prefix);
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fmt::print(f, fg(fmt::terminal_color::blue) | fmt::emphasis::bold, "{}", msg.message);
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break;
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case LogSeverity::Error:
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fmt::print(f, fg(fmt::terminal_color::bright_red), "{}", msg.prefix);
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fmt::print(f, fg(fmt::terminal_color::blue) | fmt::emphasis::bold, "{}", msg.message);
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break;
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case LogSeverity::Header:
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//fmt::print(f,"\r\x1b[2K[{}] Processing...", spinner[counter++ % 4]); fflush(f);
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fmt::print(f, fg(fmt::terminal_color::cyan) | fmt::emphasis::bold, "{}", msg.prefix);
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fmt::print(f, fg(fmt::terminal_color::white) | fmt::emphasis::bold, "{}", msg.message);
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break;
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case LogSeverity::Comment:
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case LogSeverity::Debug:
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fmt::print(f, fg(fmt::terminal_color::bright_black), "{}{}", msg.prefix, msg.message);
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break;
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case LogSeverity::Info:
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default:
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fmt::print(f, "{}{}", msg.prefix, msg.message);
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break;
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}
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}
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void yc_error_atexit()
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{
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if (!show_build_status)
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return;
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int num_errors = logger().get_errors_total();
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int num_warnings = logger().get_warnings_total();
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bool succeeded = num_errors == 0;
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if (succeeded)
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fmt::print(fg(fmt::terminal_color::bright_green), "Build succeeded: ");
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else
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fmt::print(fg(fmt::terminal_color::bright_red), "Build failed: ");
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fmt::print("{} error{}, {} warning{}\n", num_errors,
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num_errors == 1 ? "" : "s",
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num_warnings,
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num_warnings == 1 ? "" : "s");
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}
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enum class Language
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{
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Auto,
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Verilog,
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SystemVerilog,
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Vhdl
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};
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enum class SystemVerilogFrontend
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{
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Legacy,
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Slang,
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Verific
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};
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enum class VhdlFrontend
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{
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GHDL,
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Verific
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};
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enum class VerilogStandard
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{
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V1995,
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V2001,
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V2005,
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Latest = V2005
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};
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enum class SystemVerilogStandard
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{
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V2005,
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V2009,
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V2012,
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V2017,
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V2023,
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Latest = V2023
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};
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enum class VhdlStandard
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{
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V1987,
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V1993,
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V2000,
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V2008,
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V2019,
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Latest = V2019
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};
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class YosysDriver {
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public:
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CommandLine cmdLine;
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struct Options {
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std::optional<bool> showHelp;
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std::optional<bool> showVerbose;
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std::optional<bool> showVersion;
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std::optional<bool> printTargets;
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std::optional<bool> printLanguages;
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std::optional<bool> printStandards;
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std::vector<std::string> defines;
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std::vector<std::string> undefines;
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std::optional<std::string> topModule;
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std::optional<std::string> outputFile;
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std::optional<std::string> target;
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} options;
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struct Target
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{
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std::string name;
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std::string description;
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std::vector<std::string> passes;
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std::vector<std::string> files;
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};
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using SourceStandard = std::variant<
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VerilogStandard,
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SystemVerilogStandard,
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VhdlStandard
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>;
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struct SourceFile
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{
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std::string filename;
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Language language;
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SourceStandard standard;
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};
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enum class OutputFormat {
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Json,
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Verilog,
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SystemVerilog
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};
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std::vector<SourceFile> sourceFiles;
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std::vector<Target> targets;
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Language language = Language::Auto;
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VerilogStandard verilog_standard = VerilogStandard::Latest;
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SystemVerilogStandard system_verilog_standard = SystemVerilogStandard::Latest;
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VhdlStandard vhdl_standard = VhdlStandard::Latest;
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SystemVerilogFrontend system_verilog_frontend = SystemVerilogFrontend::Legacy;
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VhdlFrontend vhdl_frontend;
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OutputFormat output_format;
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void addStandardArgs();
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int run(int argc, char **argv);
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void printError(const std::string& message);
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void printHeader(const std::string& message);
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void printOption(const std::string& name, const std::string& desc);
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void registerTarget(std::string name,
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std::string description,
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std::vector<std::string> passes,
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std::vector<std::string> files)
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{
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targets.push_back({
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std::move(name),
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std::move(description),
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std::move(passes),
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std::move(files)
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});
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}
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};
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void YosysDriver::printError(const std::string& message) {
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fmt::print(stderr, fg(fmt::terminal_color::bright_red), "{}", "ERROR: ");
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fmt::print(stderr, fg(fmt::terminal_color::blue) | fmt::emphasis::bold, "{}", message);
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fmt::print(stderr, "\n");
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}
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void YosysDriver::printHeader(const std::string& message) {
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fmt::print(stderr, fg(fmt::terminal_color::white) | fmt::emphasis::bold, "{}", message);
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fmt::print(stderr, "\n");
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}
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void YosysDriver::printOption(const std::string& name, const std::string& desc) {
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fmt::print(stderr, fg(fmt::terminal_color::bright_blue) | fmt::emphasis::bold, " {:<12}", name);
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fmt::print(stderr, "- {}", desc);
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fmt::print(stderr, "\n");
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}
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static Language languageFromExtension(std::string_view filename)
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{
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auto pos = filename.rfind('.');
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if (pos == std::string_view::npos)
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return Language::Auto;
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auto extension = filename.substr(pos);
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if (extension == ".v")
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return Language::Verilog;
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if (extension == ".sv")
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return Language::SystemVerilog;
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if (extension == ".vhd" || extension == ".vhdl")
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return Language::Vhdl;
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return Language::Auto;
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}
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int YosysDriver::run(int argc, char **argv) {
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log_error_atexit = &yc_error_atexit;
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logger().add_sink<ColorLogSink>();
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registerTarget("ice40", "Lattice iCE40", {"synth_ice40"}, { "+/ice40/cells_sim.v"});
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registerTarget("ecp5", "Lattice ECP5", {"synth_ecp5"}, { "+/ecp5/cells_sim.v", "+/ecp5/cells_bb.v"});
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registerTarget("gatemate", "GateMate A1", {"synth_gatemate"}, { "+/gatemate/cells_sim.v", "+/gatemate/cells_bb.v"});
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cmdLine.add("-h,--help", options.showHelp, "Display available options");
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cmdLine.add("--version", options.showVersion, "Display version information and exit");
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cmdLine.add("-x",
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[this](std::string_view value) {
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if (value == "auto")
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language = Language::Auto;
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else if (value == "verilog")
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{
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language = Language::Verilog;
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verilog_standard = VerilogStandard::Latest;
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}
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else if (value == "sv")
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{
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language = Language::SystemVerilog;
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system_verilog_standard = SystemVerilogStandard::Latest;
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}
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else if (value == "vhdl")
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{
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language = Language::Vhdl;
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vhdl_standard = VhdlStandard::Latest;
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}
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else
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return fmt::format(
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"Invalid language '{}'; expected auto, verilog, sv or vhdl",
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value);
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return std::string{};
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},
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"Treat subsequent input files as having type <language>",
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"<language>");
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cmdLine.add("--std",
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[this](std::string_view value) {
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switch (language)
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{
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case Language::Verilog:
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if (value == "1995")
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verilog_standard = VerilogStandard::V1995;
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else if (value == "2001")
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verilog_standard = VerilogStandard::V2001;
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else if (value == "2005")
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verilog_standard = VerilogStandard::V2005;
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else
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return fmt::format(
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"Invalid Verilog standard '{}'; expected 1995, 2001 or 2005",
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value);
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break;
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case Language::SystemVerilog:
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if (value == "2005")
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system_verilog_standard = SystemVerilogStandard::V2005;
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else if (value == "2009")
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system_verilog_standard = SystemVerilogStandard::V2009;
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else if (value == "2012")
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system_verilog_standard = SystemVerilogStandard::V2012;
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else if (value == "2017")
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system_verilog_standard = SystemVerilogStandard::V2017;
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else if (value == "2023")
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system_verilog_standard = SystemVerilogStandard::V2023;
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else
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return fmt::format(
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"Invalid SystemVerilog standard '{}'; expected 2005, 2009, 2012, 2017 or 2023",
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value);
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break;
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case Language::Vhdl:
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if (value == "1987")
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vhdl_standard = VhdlStandard::V1987;
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else if (value == "1993")
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vhdl_standard = VhdlStandard::V1993;
|
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else if (value == "2000")
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vhdl_standard = VhdlStandard::V2000;
|
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else if (value == "2008")
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vhdl_standard = VhdlStandard::V2008;
|
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else if (value == "2019")
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vhdl_standard = VhdlStandard::V2019;
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else
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return fmt::format(
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"Invalid VHDL standard '{}'; expected 1987, 1993, 2000, 2008 or 2019",
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value);
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break;
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case Language::Auto:
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return std::string("Cannot specify --std when language is auto");
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}
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return std::string{};
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},
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"Language standard to compile for",
|
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"<value>");
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cmdLine.add("--front,--system-verilog-frontend",
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[this](std::string_view value) {
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if (value == "legacy")
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system_verilog_frontend = SystemVerilogFrontend::Legacy;
|
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else if (value == "slang")
|
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system_verilog_frontend = SystemVerilogFrontend::Slang;
|
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else if (value == "verific")
|
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system_verilog_frontend = SystemVerilogFrontend::Verific;
|
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else
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return fmt::format(
|
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"Invalid SystemVerilog frontend '{}'; expected legacy, slang or verific", value);
|
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|
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return std::string{};
|
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},
|
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"SystemVerilog frontend to use (legacy, slang or verific)", "<frontend>");
|
||||
|
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cmdLine.add("--vhdl-frontend",
|
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[this](std::string_view value) {
|
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if (value == "ghdl")
|
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vhdl_frontend = VhdlFrontend::GHDL;
|
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else if (value == "verific")
|
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vhdl_frontend = VhdlFrontend::Verific;
|
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else
|
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return fmt::format(
|
||||
"Invalid VHDL frontend '{}'; expected ghdl or verific", value);
|
||||
|
||||
return std::string{};
|
||||
},
|
||||
"VHDL frontend to use (ghdl or verific)", "<frontend>");
|
||||
|
||||
cmdLine.add("-o,--out",
|
||||
[this](std::string_view value) {
|
||||
options.outputFile = value;
|
||||
|
||||
auto pos = value.rfind('.');
|
||||
if (pos == std::string_view::npos)
|
||||
return fmt::format(
|
||||
"Invalid output file '{}'; expected .json, .v or .sv", value);
|
||||
|
||||
auto extension = value.substr(pos);
|
||||
|
||||
if (extension == ".json")
|
||||
output_format = OutputFormat::Json;
|
||||
else if (extension == ".v")
|
||||
output_format = OutputFormat::Verilog;
|
||||
else if (extension == ".sv")
|
||||
output_format = OutputFormat::SystemVerilog;
|
||||
else
|
||||
return fmt::format(
|
||||
"Invalid output file extension '{}'; expected .json, .v or .sv",
|
||||
extension);
|
||||
|
||||
return std::string{};
|
||||
},
|
||||
"Write the design netlist to <outfile>", "<file>");
|
||||
cmdLine.add("--top", options.topModule,
|
||||
"Top-level module to instantiate"
|
||||
"<name>");
|
||||
|
||||
cmdLine.add("--target",
|
||||
[this](std::string_view value) {
|
||||
auto it = std::find_if(targets.begin(), targets.end(),
|
||||
[value](const auto &target) {
|
||||
return target.name == value;
|
||||
});
|
||||
|
||||
if (it == targets.end())
|
||||
return fmt::format("Invalid target '{}'", value);
|
||||
|
||||
options.target = value;
|
||||
return std::string{};
|
||||
},
|
||||
"Generate netlist for the given target",
|
||||
"<value>");
|
||||
cmdLine.add("-D", options.defines,
|
||||
"Define preprocessor symbol <macro> to <value> (empty if <value> ommitted)",
|
||||
"<macro>[=<value>]",
|
||||
CommandLineFlags::CommaList);
|
||||
cmdLine.add("-U", options.undefines,
|
||||
"Undefine preprocessor symbol <macro>",
|
||||
"<macro>",
|
||||
CommandLineFlags::CommaList);
|
||||
cmdLine.add("--print-languages", options.printLanguages, "Print available languages");
|
||||
cmdLine.add("--print-standards", options.printStandards, "Print available standards for language");
|
||||
cmdLine.add("--print-targets", options.printTargets, "Print available targets");
|
||||
cmdLine.add("-v,--verbose", options.showVerbose, "Verbose output");
|
||||
cmdLine.setPositional(
|
||||
[this](std::string_view value) {
|
||||
Language fileLanguage = language;
|
||||
|
||||
if (fileLanguage == Language::Auto)
|
||||
fileLanguage = languageFromExtension(value);
|
||||
|
||||
if (fileLanguage == Language::Auto)
|
||||
return fmt::format(
|
||||
"Cannot determine language for '{}'; use -x <language>",
|
||||
value);
|
||||
|
||||
SourceStandard fileStandard;
|
||||
|
||||
switch (fileLanguage)
|
||||
{
|
||||
case Language::Verilog:
|
||||
fileStandard = verilog_standard;
|
||||
break;
|
||||
|
||||
case Language::SystemVerilog:
|
||||
fileStandard = system_verilog_standard;
|
||||
break;
|
||||
|
||||
case Language::Vhdl:
|
||||
fileStandard = vhdl_standard;
|
||||
break;
|
||||
|
||||
case Language::Auto:
|
||||
// Handled above.
|
||||
return std::string{};
|
||||
}
|
||||
sourceFiles.push_back({
|
||||
std::string(value),
|
||||
fileLanguage,
|
||||
fileStandard
|
||||
});
|
||||
return std::string{};
|
||||
},
|
||||
"files");
|
||||
|
||||
log_suppressed();
|
||||
|
||||
if (!cmdLine.parse(argc, argv, {})) {
|
||||
for (auto& err : cmdLine.getErrors()) {
|
||||
printError(err.message.c_str());
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (options.showVerbose) {
|
||||
is_verbose = true;
|
||||
}
|
||||
|
||||
if (options.showHelp) {
|
||||
fmt::print(stderr, "{}\n", cmdLine.getHelpText("Yosys compiler"));
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (options.showVersion) {
|
||||
fmt::print(stderr, "{}\n", yosys_version_str);
|
||||
return 0;
|
||||
}
|
||||
if (options.printLanguages) {
|
||||
printHeader("Registered Languages:");
|
||||
printOption("verilog", "Verilog");
|
||||
printOption("sv", "SystemVerilog");
|
||||
printOption("vhdl", "VHDL");
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (options.printStandards) {
|
||||
switch (language) {
|
||||
case Language::Verilog:
|
||||
printHeader("Registered Standards for verilog:");
|
||||
printOption("1995", "Verilog 1364-1995");
|
||||
printOption("2001", "Verilog 1364-2001");
|
||||
printOption("2005", "Verilog 1364-2005");
|
||||
break;
|
||||
|
||||
case Language::SystemVerilog:
|
||||
printHeader("Registered Standards for sv:");
|
||||
printOption("2005", "SystemVerilog 1800-2005");
|
||||
printOption("2009", "SystemVerilog 1800-2009");
|
||||
printOption("2012", "SystemVerilog 1800-2012");
|
||||
printOption("2017", "SystemVerilog 1800-2017");
|
||||
printOption("2023", "SystemVerilog 1800-2023");
|
||||
break;
|
||||
|
||||
case Language::Vhdl:
|
||||
printHeader("Registered Standards for vhdl:");
|
||||
printOption("1987", "VHDL 1987");
|
||||
printOption("1993", "VHDL 1993");
|
||||
printOption("2000", "VHDL 2000");
|
||||
printOption("2008", "VHDL 2008");
|
||||
printOption("2019", "VHDL 2019");
|
||||
break;
|
||||
|
||||
case Language::Auto:
|
||||
printHeader("Registered Standards:");
|
||||
printOption("verilog", "Use -x verilog to list Verilog standards");
|
||||
printOption("sv", "Use -x sv to list SystemVerilog standards");
|
||||
printOption("vhdl", "Use -x vhdl to list VHDL standards");
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (options.printTargets) {
|
||||
printHeader("Registered Targets:");
|
||||
|
||||
for (const auto &target : targets)
|
||||
printOption(target.name, target.description);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!options.target) {
|
||||
printError("target is not specified.");
|
||||
return 1;
|
||||
}
|
||||
if (!sourceFiles.size()) {
|
||||
printError("no input files");
|
||||
return 1;
|
||||
}
|
||||
if (!options.outputFile) {
|
||||
printError("no output file");
|
||||
return 1;
|
||||
}
|
||||
if (!options.topModule) {
|
||||
printError("no top module specified");
|
||||
return 1;
|
||||
}
|
||||
|
||||
show_build_status = true;
|
||||
std::vector<std::string> passes;
|
||||
|
||||
if (!options.defines.empty()) {
|
||||
for (auto vdef : options.defines) {
|
||||
switch (system_verilog_frontend)
|
||||
{
|
||||
case SystemVerilogFrontend::Legacy:
|
||||
passes.push_back(stringf("verilog_defines -D %s", vdef));
|
||||
break;
|
||||
|
||||
case SystemVerilogFrontend::Slang:
|
||||
//
|
||||
break;
|
||||
|
||||
case SystemVerilogFrontend::Verific:
|
||||
passes.push_back(stringf("verific -vlog-define %s", vdef));
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!options.undefines.empty()) {
|
||||
for (auto vdef : options.undefines)
|
||||
passes.push_back("read -undef " + vdef);
|
||||
}
|
||||
|
||||
auto it = std::find_if(targets.begin(), targets.end(),
|
||||
[this](const auto &target) {
|
||||
return target.name == options.target;
|
||||
});
|
||||
|
||||
std::string files;
|
||||
for (const auto &f : it->files) {
|
||||
std::string fn = f;
|
||||
rewrite_filename(fn);
|
||||
|
||||
if (!files.empty())
|
||||
files += ' ';
|
||||
|
||||
files += fn;
|
||||
}
|
||||
switch (system_verilog_frontend)
|
||||
{
|
||||
case SystemVerilogFrontend::Legacy:
|
||||
passes.push_back(stringf("read_verilog -lib -specify %s", files));
|
||||
break;
|
||||
|
||||
case SystemVerilogFrontend::Slang:
|
||||
passes.push_back(stringf("read_slang %s", files));
|
||||
break;
|
||||
|
||||
case SystemVerilogFrontend::Verific:
|
||||
passes.push_back(stringf("verific -vlog-incdir -I /home/micko/src/yosys/build/share/ecp5"));
|
||||
passes.push_back(stringf("verific -sv -lib %s ", files));
|
||||
break;
|
||||
}
|
||||
|
||||
for (const auto &file : sourceFiles)
|
||||
{
|
||||
switch (file.language)
|
||||
{
|
||||
case Language::Verilog:
|
||||
switch (system_verilog_frontend)
|
||||
{
|
||||
case SystemVerilogFrontend::Legacy:
|
||||
passes.push_back(stringf("read_verilog %s", file.filename));
|
||||
break;
|
||||
|
||||
case SystemVerilogFrontend::Slang:
|
||||
passes.push_back(stringf("read_slang --allow-use-before-declare %s", file.filename));
|
||||
break;
|
||||
|
||||
case SystemVerilogFrontend::Verific:
|
||||
passes.push_back(stringf("verific -vlog95 %s", file.filename));
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case Language::SystemVerilog:
|
||||
switch (system_verilog_frontend)
|
||||
{
|
||||
case SystemVerilogFrontend::Legacy:
|
||||
passes.push_back(stringf("read_verilog -sv %s", file.filename));
|
||||
break;
|
||||
|
||||
case SystemVerilogFrontend::Slang:
|
||||
passes.push_back(stringf("read_slang --allow-use-before-declare %s", file.filename));
|
||||
break;
|
||||
|
||||
case SystemVerilogFrontend::Verific:
|
||||
passes.push_back(stringf("verific -sv %s", file.filename));
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case Language::Vhdl:
|
||||
switch (vhdl_frontend)
|
||||
{
|
||||
case VhdlFrontend::GHDL:
|
||||
passes.push_back(stringf("ghdl %s", file.filename));
|
||||
break;
|
||||
|
||||
case VhdlFrontend::Verific:
|
||||
passes.push_back(stringf("verific -vhdl %s", file.filename));
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case Language::Auto:
|
||||
// Should never occur; resolved when SourceFile was created.
|
||||
break;
|
||||
}
|
||||
}
|
||||
passes.push_back(stringf("hierarchy -top %s", options.topModule.value()));
|
||||
|
||||
for (const auto &pass : it->passes) {
|
||||
// run pass
|
||||
passes.push_back(pass);
|
||||
}
|
||||
|
||||
switch (output_format) {
|
||||
case OutputFormat::Json:
|
||||
passes.push_back(stringf("write_json %s", options.outputFile.value()));
|
||||
break;
|
||||
case OutputFormat::Verilog:
|
||||
passes.push_back(stringf("write_verilog %s", options.outputFile.value()));
|
||||
break;
|
||||
case OutputFormat::SystemVerilog:
|
||||
passes.push_back(stringf("write_verilog -sv %s", options.outputFile.value()));
|
||||
break;
|
||||
}
|
||||
|
||||
for(auto &p : passes) {
|
||||
//printf("%s\n",p.c_str());
|
||||
run_pass(p);
|
||||
}
|
||||
yosys_design->check();
|
||||
for (auto it : saved_designs)
|
||||
it.second->check();
|
||||
for (auto it : pushed_designs)
|
||||
it->check();
|
||||
|
||||
yc_error_atexit();
|
||||
log_flush();
|
||||
return 0;
|
||||
}
|
||||
|
||||
YOSYS_NAMESPACE_END
|
||||
|
||||
|
||||
USING_YOSYS_NAMESPACE
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
yosys_setup();
|
||||
YosysDriver driver;
|
||||
int ret = driver.run(argc, argv);
|
||||
yosys_shutdown();
|
||||
return ret;
|
||||
}
|
||||
Reference in New Issue
Block a user