mirror of https://github.com/YosysHQ/yosys.git
inital extract_reduce tests
This commit is contained in:
williamzhu17
parent
bbd132f6ba
commit
8f5f4ecab4
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@ -0,0 +1,605 @@
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###################################################################
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# Extract Reduce AND Gates Tests
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###################################################################
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log -header "Simple AND chain"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [3:0] a,
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output wire x
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);
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assign x = a[0] & a[1] & a[2] & a[3];
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$and
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select -assert-count 1 t:$reduce_and
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design -reset
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log -pop
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log -header "AND chain with multiple branches"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [5:0] a,
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output wire x
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);
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wire w1, w2, w3, w4;
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assign w1 = a[0] & a[1];
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assign w2 = a[2] & a[3];
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assign w3 = a[4] & a[5];
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assign w4 = w1 & w2;
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assign x = w3 & w4;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$and
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select -assert-count 1 t:$reduce_and
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design -reset
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log -pop
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log -header "No off-chain"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [4:0] a,
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output wire x,
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output wire y
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);
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wire w1, w2, w3;
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assign w1 = a[0] & a[1];
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assign w2 = w1 & a[2];
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assign w3 = w2 & a[3];
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assign x = w3 & a[4];
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// Off-chain use of w2
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assign y = w2;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$and
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select -assert-count 2 t:$reduce_and
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# Check that both gates are 3 bits wide
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select -assert-none t:$reduce_and r:A_WIDTH!=3 %i
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design -reset
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log -pop
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log -header "Allow off-chain for AND"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [4:0] a,
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output wire x,
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output wire y
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);
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wire w1, w2, w3;
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assign w1 = a[0] & a[1];
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assign w2 = w1 & a[2];
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assign w3 = w2 & a[3];
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assign x = w3 & a[4];
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// Off-chain use of w2
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assign y = w2;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce -allow-off-chain
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$and
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select -assert-count 2 t:$reduce_and
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# Check that only one gate has a width of 5 and one gate has a width of 3
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select -assert-count 1 t:$reduce_and r:A_WIDTH=5 %i
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select -assert-count 1 t:$reduce_and r:A_WIDTH=3 %i
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design -reset
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log -pop
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###################################################################
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# Extract Reduce OR Gates Tests
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###################################################################
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log -header "Simple OR chain"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [3:0] a,
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output wire x
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);
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assign x = a[0] | a[1] | a[2] | a[3];
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$or
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select -assert-count 1 t:$reduce_or
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design -reset
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log -pop
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log -header "OR chain with multiple branches"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [5:0] a,
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output wire x
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);
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wire w1, w2, w3, w4;
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assign w1 = a[0] | a[1];
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assign w2 = a[2] | a[3];
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assign w3 = a[4] | a[5];
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assign w4 = w1 | w2;
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assign x = w3 | w4;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$or
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select -assert-count 1 t:$reduce_or
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design -reset
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log -pop
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log -header "No off-chain OR"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [4:0] a,
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output wire x,
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output wire y
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);
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wire w1, w2, w3;
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assign w1 = a[0] | a[1];
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assign w2 = w1 | a[2];
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assign w3 = w2 | a[3];
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assign x = w3 | a[4];
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// Off-chain use of w2
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assign y = w2;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$or
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select -assert-count 2 t:$reduce_or
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# Check that both gates are 3 bits wide
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select -assert-none t:$reduce_or r:A_WIDTH!=3 %i
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design -reset
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log -pop
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log -header "Allow off-chain for OR"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [4:0] a,
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output wire x,
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output wire y
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);
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wire w1, w2, w3;
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assign w1 = a[0] | a[1];
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assign w2 = w1 | a[2];
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assign w3 = w2 | a[3];
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assign x = w3 | a[4];
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// Off-chain use of w2
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assign y = w2;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce -allow-off-chain
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$or
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select -assert-count 2 t:$reduce_or
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# Check that only one gate has a width of 5 and one gate has a width of 3
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select -assert-count 1 t:$reduce_or r:A_WIDTH=5 %i
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select -assert-count 1 t:$reduce_or r:A_WIDTH=3 %i
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design -reset
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log -pop
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###################################################################
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# Extract Reduce XOR Gates Tests
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###################################################################
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log -header "Simple XOR chain"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [3:0] a,
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output wire x
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);
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assign x = a[0] ^ a[1] ^ a[2] ^ a[3];
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$xor
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select -assert-count 1 t:$reduce_xor
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design -reset
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log -pop
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log -header "XOR chain with multiple branches"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [5:0] a,
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output wire x
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);
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wire w1, w2, w3, w4;
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assign w1 = a[0] ^ a[1];
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assign w2 = a[2] ^ a[3];
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assign w3 = a[4] ^ a[5];
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assign w4 = w1 ^ w2;
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assign x = w3 ^ w4;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$xor
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select -assert-count 1 t:$reduce_xor
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design -reset
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log -pop
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log -header "No off-chain XOR"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [4:0] a,
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output wire x,
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output wire y
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);
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wire w1, w2, w3;
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assign w1 = a[0] ^ a[1];
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assign w2 = w1 ^ a[2];
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assign w3 = w2 ^ a[3];
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assign x = w3 ^ a[4];
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// Off-chain use of w2
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assign y = w2;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$xor
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select -assert-count 2 t:$reduce_xor
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# Check that both gates are 3 bits wide
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select -assert-none t:$reduce_xor r:A_WIDTH!=3 %i
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design -reset
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log -pop
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log -header "Allow off-chain for XOR"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [4:0] a,
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output wire x,
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output wire y
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);
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wire w1, w2, w3;
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assign w1 = a[0] ^ a[1];
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assign w2 = w1 ^ a[2];
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assign w3 = w2 ^ a[3];
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assign x = w3 ^ a[4];
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// Off-chain use of w2
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assign y = w2;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce -allow-off-chain
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$xor
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select -assert-count 2 t:$reduce_xor
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# Check that only one gate has a width of 5 and one gate has a width of 3
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select -assert-count 1 t:$reduce_xor r:A_WIDTH=5 %i
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select -assert-count 1 t:$reduce_xor r:A_WIDTH=3 %i
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design -reset
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log -pop
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###################################################################
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# Extract PMUX from MUX Chains Tests
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###################################################################
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log -header "Simple MUX chain to PMUX"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [2:0] sel,
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input wire [3:0] a,
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output wire x
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);
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wire w1, w2;
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assign w1 = sel[0] ? a[1] : a[0];
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assign w2 = sel[1] ? a[2] : w1;
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assign x = sel[2] ? a[3] : w2;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check we got a single pmux
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select -assert-count 0 t:$mux
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select -assert-count 1 t:$pmux
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design -reset
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log -pop
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# TODO
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log -header "MUX chain with multiple branches"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [2:0] sel,
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input wire [3:0] a,
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output wire x
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);
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wire w1, w2;
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assign w1 = sel[0] ? a[1] : a[0];
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assign w2 = sel[1] ? a[2] : a[3];
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assign x = sel[2] ? w1 : w2;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check we got a single pmux
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select -assert-count 0 t:$mux
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select -assert-count 1 t:$pmux
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design -reset
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log -pop
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log -header "No off-chain MUX chain"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [3:0] sel,
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input wire [4:0] a,
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output wire x,
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output wire y
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);
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wire w1, w2, w3;
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assign w1 = sel[0] ? a[1] : a[0];
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assign w2 = sel[1] ? a[2] : w1;
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assign w3 = sel[2] ? a[3] : w2;
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assign x = sel[3] ? a[4] : w3;
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// Off-chain use of intermediate wire
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assign y = w2;
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endmodule
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EOF
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check -assert
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|
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# Check equivalence after extract_reduce
|
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equiv_opt -assert extract_reduce
|
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|
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# Load design and run opt_clean to remove unnecessary wires
|
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design -load postopt
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opt_clean
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|
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# Check we got two pmuxes
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select -assert-count 0 t:$mux
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select -assert-count 2 t:$pmux
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# Check that both pmuxes have input width of 3
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select -assert-none t:$pmux r:S_WIDTH!=3 %i
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|
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design -reset
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log -pop
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|
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log -header "Allow off-chain MUX chain"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [3:0] sel,
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input wire [4:0] a,
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output wire x,
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||||
output wire y
|
||||
);
|
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wire w1, w2, w3;
|
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|
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assign w1 = sel[0] ? a[1] : a[0];
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assign w2 = sel[1] ? a[2] : w1;
|
||||
assign w3 = sel[2] ? a[3] : w2;
|
||||
assign x = sel[3] ? a[4] : w3;
|
||||
|
||||
assign y = w2;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after extract_reduce
|
||||
equiv_opt -assert extract_reduce -allow-off-chain
|
||||
|
||||
# Load design and run opt_clean to remove unnecessary wires
|
||||
design -load postopt
|
||||
opt_clean
|
||||
|
||||
# Check we got two $pmux
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 2 t:$pmux
|
||||
|
||||
# Check that one pmux has an input width of 3
|
||||
# and the other has an input width of 5
|
||||
select -assert-count 1 t:$pmux r:S_WIDTH=3 %i
|
||||
select -assert-count 1 t:$pmux r:S_WIDTH=5 %i
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
Loading…
Reference in New Issue