From 8f5b20c423a70d9ce36acccb99e489f96427c8ce Mon Sep 17 00:00:00 2001
From: Akash Levy <akashlevy@gmail.com>
Date: Thu, 11 Sep 2025 04:46:32 -0700
Subject: [PATCH] Apply suggestions from code review

Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com>
---
 tests/peepopt/addsub_c.ys | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/tests/peepopt/addsub_c.ys b/tests/peepopt/addsub_c.ys
index 6543de7cf..9a6a397cb 100644
--- a/tests/peepopt/addsub_c.ys
+++ b/tests/peepopt/addsub_c.ys
@@ -81,7 +81,7 @@ log -push
 read_verilog <<EOT
 module top(
 	input signed [3:0] a,
-	output signed [7:0] y,
+	output signed [7:0] y
 );
 	wire signed [7:0] add;
 	assign add = a + 4'sd6;
@@ -100,7 +100,7 @@ log -push
 read_verilog <<EOT
 module top(
 	input signed [3:0] a,
-	output signed [7:0] y,
+	output signed [7:0] y
 );
 	wire signed [7:0] add;
 	assign add = a + 4'sd6;
@@ -119,7 +119,7 @@ log -push
 read_verilog <<EOT
 module top(
 	input signed [3:0] a,
-	output signed [7:0] y,
+	output signed [7:0] y
 );
 	wire signed [7:0] sub;
 	assign sub = a - 4'sd6;
@@ -138,7 +138,7 @@ log -push
 read_verilog <<EOT
 module top(
 	input signed [3:0] a,
-	output signed [7:0] y,
+	output signed [7:0] y
 );
 	wire signed [7:0] sub;
 	assign sub = a - 4'sd6;
@@ -159,7 +159,7 @@ log -push
 read_verilog <<EOT
 module top(
 	input signed [3:0] a,
-	output signed [7:0] y,
+	output signed [7:0] y
 );
 	wire signed [7:0] add;
 	assign add = 4'sd6 + a;