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https://github.com/YosysHQ/yosys.git
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WIP
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@@ -71,7 +71,7 @@ struct LatticeGsrPass : public Pass {
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if (found_gsr)
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log_error("Found more than one GSR or SGSR cell in module %s.\n", module);
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found_gsr = true;
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SigSpec sig_gsr = cell->getPort(ID(GSR));
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SigSpec sig_gsr = cell->getPort(TW::GSR);
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if (GetSize(sig_gsr) < 1)
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log_error("GSR cell %s has disconnected GSR input.\n", cell);
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gsr = sigmap(sig_gsr[0]);
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@@ -118,14 +118,14 @@ struct LatticeGsrPass : public Pass {
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continue;
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if (cell->getParam(ID(SRMODE)).decode_string() != "ASYNC")
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continue;
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SigSpec sig_lsr = cell->getPort(ID(LSR));
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SigSpec sig_lsr = cell->getPort(TW::LSR);
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if (GetSize(sig_lsr) < 1)
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continue;
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SigBit lsr = sigmap(sig_lsr[0]);
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if (!inverted_gsr.count(lsr))
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continue;
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cell->setParam(ID(SRMODE), Const("LSR_OVER_CE"));
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cell->unsetPort(ID(LSR));
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cell->unsetPort(TW::LSR);
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}
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}
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