tests: tidy up testcase

2026-10-06 10:03:36 +02:00 · 2020-06-03 08:41:55 -07:00
parent 00c5ceb1f2
commit 8a11019d38
1 changed files with 0 additions and 3 deletions
@@ -7,9 +7,6 @@ always @*
 assign q = ~l;
 endmodule
 EOT
-proc
-design -save gold
-
 # Can't run any sort of equivalence check because latches are blown to LUTs
 synth_ecp5 -abc9
 select -assert-count 2 t:LUT4