From 877e97de061a66d0d4c5a4b1f220f5b6999e214a Mon Sep 17 00:00:00 2001 From: AdvaySingh1 Date: Fri, 27 Feb 2026 15:23:50 -0800 Subject: [PATCH] Changed to for chacterization --- passes/techmap/clockgate.cc | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/passes/techmap/clockgate.cc b/passes/techmap/clockgate.cc index 6a5f95d5b..ca7d01ec3 100644 --- a/passes/techmap/clockgate.cc +++ b/passes/techmap/clockgate.cc @@ -395,9 +395,12 @@ struct ClockgatePass : public Pass { // Fix CE polarity if needed if (!clk.pol_ce) { Wire *ce_not_wire = module->addWire(NEW_ID2_SUFFIX("ce_not_w")); - Cell *ce_not = module->addCell(NEW_ID2_SUFFIX("ce_not"), ID($_NOT_)); - ce_not->setPort(ID::A, clk.ce_bit); - ce_not->setPort(ID::Y, ce_not_wire); + Cell *ce_not = module->addCell(NEW_ID2_SUFFIX("ce_not"), ID($not)); + ce_not->setParam(ID::A_SIGNED, 0); + ce_not->setParam(ID::A_WIDTH, 1); + ce_not->setParam(ID::Y_WIDTH, 1); + ce_not->setPort(ID::A, clk.ce_bit); + ce_not->setPort(ID::Y, ce_not_wire); gclk.ce_not_cell = ce_not; icg->setPort(matching_icg_desc->ce_pin, ce_not_wire); }