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Merge pull request #6090 from YosysHQ/emil/hierarchy-fix-keep-cache-again 

hierarchy: fix keep cache usage by caching false too 2
This commit is contained in:
Emil J 2026-08-05 21:54:55 +00:00 committed by GitHub
parent c2071b80ed 253388a87f
commit 72ce1b63d7
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GPG Key ID: B5690EEEBB952194
4 changed files with 71 additions and 6 deletions
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20
passes/hierarchy/hierarchy.cc
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@ -684,23 +684,31 @@ void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib)
bool set_keep_print(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod) bool set_keep_print(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
{ {
if (cache.count(mod) == 0) if (cache.count(mod) == 0) {
cache[mod] = false;
for (auto c : mod->cells()) { for (auto c : mod->cells()) {
RTLIL::Module *m = mod->design->module(c->type); RTLIL::Module *m = mod->design->module(c->type);
if ((m != nullptr && set_keep_print(cache, m)) || c->type == ID($print)) if ((m != nullptr && set_keep_print(cache, m)) || c->type == ID($print)) {
return cache[mod] = true; cache[mod] = true;
break;
}
} }
}
return cache[mod]; return cache[mod];
} }
bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod) bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
{ {
if (cache.count(mod) == 0) if (cache.count(mod) == 0) {
cache[mod] = false;
for (auto c : mod->cells()) { for (auto c : mod->cells()) {
RTLIL::Module *m = mod->design->module(c->type); RTLIL::Module *m = mod->design->module(c->type);
if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in(ID($check), ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in(ID($check), ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) {
return cache[mod] = true; cache[mod] = true;
break;
}
} }
}
return cache[mod]; return cache[mod];
} }

48
tests/various/hierarchy_keep.ys Normal file
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@ -0,0 +1,48 @@
read_verilog -noblackbox <<EOT
module top;
sub s0();
foo f0();
endmodule
module foo;
sub s0();
initial
$display("hello");
endmodule
module sub;
endmodule
EOT
design -save print
hierarchy -top top
select -assert-any top A:keep %i
design -reset
design -load print
hierarchy -nokeep_prints -top top
select -assert-none top A:keep %i
design -reset
read_verilog -sv -noblackbox <<EOT
module top;
sub s0();
foo f0();
endmodule
module foo;
sub s0();
initial
assert(false);
endmodule
module sub;
endmodule
EOT
design -save print
hierarchy -top top
select -assert-any top A:keep %i
design -reset
design -load print
hierarchy -nokeep_asserts -top top
select -assert-none top A:keep %i

3
tests/various/hierarchy_recursive.v Normal file
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@ -0,0 +1,3 @@
module top(input x, output y);
top top_i(.x(x), .y(y));
endmodule

6
tests/various/hierarchy_recursive.ys Normal file
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@ -0,0 +1,6 @@
read_verilog <<EOT
module top(input x, output y);
top top_i(.x(x), .y(y));
endmodule
EOT
hierarchy