mirror of https://github.com/YosysHQ/yosys.git
49 lines
716 B
Plaintext
49 lines
716 B
Plaintext
read_verilog -noblackbox <<EOT
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module top;
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sub s0();
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foo f0();
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endmodule
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module foo;
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sub s0();
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initial
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$display("hello");
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endmodule
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module sub;
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endmodule
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EOT
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design -save print
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hierarchy -top top
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select -assert-any top A:keep %i
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design -reset
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design -load print
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hierarchy -nokeep_prints -top top
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select -assert-none top A:keep %i
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design -reset
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read_verilog -sv -noblackbox <<EOT
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module top;
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sub s0();
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foo f0();
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endmodule
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module foo;
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sub s0();
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initial
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assert(false);
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endmodule
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module sub;
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endmodule
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EOT
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design -save print
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hierarchy -top top
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select -assert-any top A:keep %i
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design -reset
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design -load print
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hierarchy -nokeep_asserts -top top
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select -assert-none top A:keep %i
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