From 727c6a51be2c0fa1a457faa0149f2adc4f12d8e5 Mon Sep 17 00:00:00 2001
From: williamzhu17 <williammzhu@gmail.com>
Date: Fri, 28 Mar 2025 14:54:00 -0700
Subject: [PATCH] added comment about one test case

---
 tests/silimate/breaksop.ys | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/tests/silimate/breaksop.ys b/tests/silimate/breaksop.ys
index dda8aff6c..42a305e04 100644
--- a/tests/silimate/breaksop.ys
+++ b/tests/silimate/breaksop.ys
@@ -114,6 +114,9 @@ select -assert-count 1 t:$sop
 equiv_opt -assert breaksop
 
 # Check final design has correct number of gates
+# We only have one AND gate since breaksop turns the OR gate into an AND gate
+# The inputs to this gate are inverted and the outputs are also inverted, so with 
+# DeMorgan's law, they are equivalent
 design -load postopt
 opt     # Run opt to remove unneeded OR gate
 select -assert-count 1 t:$reduce_and