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yosys
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Merge branch 'YosysHQ:main' into main

This commit is contained in:
Akash Levy 2025-11-24 14:04:13 -05:00 committed by GitHub
parent a705042d2e 510f9ef63d
commit 71ba176b50
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GPG Key ID: B5690EEEBB952194
8 changed files with 37 additions and 6 deletions
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5
Makefile
View File

@ -177,7 +177,7 @@ ifeq ($(OS), Haiku)
CXXFLAGS += -D_DEFAULT_SOURCE
endif
YOSYS_VER := 0.59+110
YOSYS_VER := 0.59+117
YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1)
YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2)
YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'.' -f3)
@ -497,6 +497,9 @@ else
ifeq ($(ABCEXTERNAL),)
TARGETS := $(PROGRAM_PREFIX)yosys-abc$(EXE) $(TARGETS)
endif
ifeq ($(DISABLE_SPAWN),1)
$(error ENABLE_ABC=1 requires either LINK_ABC=1 or DISABLE_SPAWN=0)
endif
endif
endif

3
frontends/aiger2/xaiger.cc
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@ -110,7 +110,8 @@ struct Xaiger2Frontend : public Frontend {
for (int i = 0; i < (int) O; i++) {
int po;
*f >> po;
log_assert(f->get() == '\n');
int c = f->get();
log_assert(c == '\n');
outputs.push_back(po);
}

9
passes/cmds/sdc/sdc.cc
View File

@ -8,6 +8,11 @@
#include <optional>
#include <iostream>
#if TCL_MAJOR_VERSION < 9
typedef int YS_Tcl_Size;
#else
typedef Tcl_Size YS_Tcl_Size;
#endif
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
@ -432,7 +437,7 @@ static size_t get_node_count(Tcl_Interp* interp) {
std::vector<std::vector<std::string>> gather_nested_calls(Tcl_Interp* interp) {
Tcl_Obj* listObj = Tcl_GetVar2Ex(interp, "sdc_calls", nullptr, TCL_GLOBAL_ONLY);
int listLength;
YS_Tcl_Size listLength;
std::vector<std::vector<std::string>> sdc_calls;
if (Tcl_ListObjLength(interp, listObj, &listLength) == TCL_OK) {
@ -442,7 +447,7 @@ std::vector<std::vector<std::string>> gather_nested_calls(Tcl_Interp* interp) {
if (Tcl_ListObjIndex(interp, listObj, i, &subListObj) != TCL_OK) {
log_error("broken list of lists\n");
}
int subListLength;
YS_Tcl_Size subListLength;
if (Tcl_ListObjLength(interp, subListObj, &subListLength) == TCL_OK) {
// Valid list - extract elements
for (int j = 0; j < subListLength; j++) {

2
passes/techmap/abc.cc
View File

@ -1059,7 +1059,7 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module
abc_script += stringf("; write_blif %s/output.blif", run_abc.tempdir_name);
abc_script = add_echos_to_abc_cmd(abc_script);
#if defined(__linux__) && !defined(YOSYS_DISABLE_SPAWN)
abc_script += "; echo \"YOSYS_ABC_DONE\"\n";
abc_script += "; echo; echo \"YOSYS_ABC_DONE\"\n";
#endif
for (size_t i = 0; i+1 < abc_script.size(); i++)

3
passes/techmap/abc_new.cc
View File

@ -38,7 +38,8 @@ std::vector<Module*> order_modules(Design *design, std::vector<Module *> modules
sort.edge(submodule, m);
}
}
log_assert(sort.sort());
bool is_sorted = sort.sort();
log_assert(is_sorted);
return sort.sorted;
}

2
tests/techmap/bug5495.abc Normal file
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@ -0,0 +1,2 @@
fraig_store; fraig_restore

12
tests/techmap/bug5495.sh Executable file
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@ -0,0 +1,12 @@
#!/usr/bin/env bash
if ! which timeout ; then
echo "No 'timeout', skipping test"
exit 0
fi
if ! timeout 5 ../../yosys bug5495.v -p 'hierarchy; techmap; abc -script bug5495.abc' ; then
echo "Yosys failed to complete"
exit 1
fi

7
tests/techmap/bug5495.v Normal file
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@ -0,0 +1,7 @@
module simple(I1, I2, O);
input wire I1;
input wire I2;
output wire O;
assign O = I1 | I2;
endmodule