diff --git a/Makefile b/Makefile
index 8f4eb61d8..379c57708 100644
--- a/Makefile
+++ b/Makefile
@@ -177,7 +177,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.59+110
+YOSYS_VER := 0.59+117
 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1)
 YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2)
 YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'.' -f3)
@@ -497,6 +497,9 @@ else
 ifeq ($(ABCEXTERNAL),)
 TARGETS := $(PROGRAM_PREFIX)yosys-abc$(EXE) $(TARGETS)
 endif
+ifeq ($(DISABLE_SPAWN),1)
+$(error ENABLE_ABC=1 requires either LINK_ABC=1 or DISABLE_SPAWN=0)
+endif
 endif
 endif
 
diff --git a/frontends/aiger2/xaiger.cc b/frontends/aiger2/xaiger.cc
index d983f8c41..510da0be8 100644
--- a/frontends/aiger2/xaiger.cc
+++ b/frontends/aiger2/xaiger.cc
@@ -110,7 +110,8 @@ struct Xaiger2Frontend : public Frontend {
 		for (int i = 0; i < (int) O; i++) {
 			int po;
 			*f >> po;
-			log_assert(f->get() == '\n');
+			int c = f->get();
+			log_assert(c == '\n');
 			outputs.push_back(po);
 		}
 
diff --git a/passes/cmds/sdc/sdc.cc b/passes/cmds/sdc/sdc.cc
index eb1951665..fad001e50 100644
--- a/passes/cmds/sdc/sdc.cc
+++ b/passes/cmds/sdc/sdc.cc
@@ -8,6 +8,11 @@
 #include <optional>
 #include <iostream>
 
+#if TCL_MAJOR_VERSION < 9
+typedef int YS_Tcl_Size;
+#else
+typedef Tcl_Size YS_Tcl_Size;
+#endif
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
@@ -432,7 +437,7 @@ static size_t get_node_count(Tcl_Interp* interp) {
 std::vector<std::vector<std::string>> gather_nested_calls(Tcl_Interp* interp) {
 
 	Tcl_Obj* listObj = Tcl_GetVar2Ex(interp, "sdc_calls", nullptr, TCL_GLOBAL_ONLY);
-	int listLength;
+	YS_Tcl_Size listLength;
 
 	std::vector<std::vector<std::string>> sdc_calls;
 	if (Tcl_ListObjLength(interp, listObj, &listLength) == TCL_OK) {
@@ -442,7 +447,7 @@ std::vector<std::vector<std::string>> gather_nested_calls(Tcl_Interp* interp) {
 			if (Tcl_ListObjIndex(interp, listObj, i, &subListObj) != TCL_OK) {
 				log_error("broken list of lists\n");
 			}
-			int subListLength;
+			YS_Tcl_Size subListLength;
 			if (Tcl_ListObjLength(interp, subListObj, &subListLength) == TCL_OK) {
 				// Valid list - extract elements
 				for (int j = 0; j < subListLength; j++) {
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 29d0cb0f2..6a1aa20cd 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -1059,7 +1059,7 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module
 	abc_script += stringf("; write_blif %s/output.blif", run_abc.tempdir_name);
 	abc_script = add_echos_to_abc_cmd(abc_script);
 #if defined(__linux__) && !defined(YOSYS_DISABLE_SPAWN)
-	abc_script += "; echo \"YOSYS_ABC_DONE\"\n";
+	abc_script += "; echo; echo \"YOSYS_ABC_DONE\"\n";
 #endif
 
 	for (size_t i = 0; i+1 < abc_script.size(); i++)
diff --git a/passes/techmap/abc_new.cc b/passes/techmap/abc_new.cc
index 21ffa075b..4e279c577 100644
--- a/passes/techmap/abc_new.cc
+++ b/passes/techmap/abc_new.cc
@@ -38,7 +38,8 @@ std::vector<Module*> order_modules(Design *design, std::vector<Module *> modules
 				sort.edge(submodule, m);
 		}
 	}
-	log_assert(sort.sort());
+	bool is_sorted = sort.sort();
+	log_assert(is_sorted);
 	return sort.sorted;
 }
 
diff --git a/tests/techmap/bug5495.abc b/tests/techmap/bug5495.abc
new file mode 100644
index 000000000..60a29a58a
--- /dev/null
+++ b/tests/techmap/bug5495.abc
@@ -0,0 +1,2 @@
+
+fraig_store; fraig_restore
diff --git a/tests/techmap/bug5495.sh b/tests/techmap/bug5495.sh
new file mode 100755
index 000000000..64bf2ca99
--- /dev/null
+++ b/tests/techmap/bug5495.sh
@@ -0,0 +1,12 @@
+#!/usr/bin/env bash
+
+if ! which timeout ; then
+    echo "No 'timeout', skipping test"
+    exit 0
+fi
+
+if ! timeout 5 ../../yosys bug5495.v -p 'hierarchy; techmap; abc -script bug5495.abc' ; then
+    echo "Yosys failed to complete"
+    exit 1
+fi
+
diff --git a/tests/techmap/bug5495.v b/tests/techmap/bug5495.v
new file mode 100644
index 000000000..37ce73ec8
--- /dev/null
+++ b/tests/techmap/bug5495.v
@@ -0,0 +1,7 @@
+module simple(I1, I2, O);
+	input wire I1;
+	input wire I2;
+	output wire O;
+
+	assign O = I1 | I2;
+endmodule