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Document always_latch.

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nella 2026-07-14 10:39:58 +02:00
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docs/source/using_yosys/verilog.rst
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@ -172,7 +172,10 @@ Verilog Attributes and non-standard features
- The frontend sets attributes ``always_comb``, ``always_latch`` and - The frontend sets attributes ``always_comb``, ``always_latch`` and
``always_ff`` on processes derived from SystemVerilog style always blocks ``always_ff`` on processes derived from SystemVerilog style always blocks
according to the type of the always. These are checked for correctness in according to the type of the always. These are checked for correctness in
``proc_dlatch``. ``proc_dlatch``. Latches inferred from ``always_latch`` processes are exempt
from the ``proc -latches <info|warn|error>`` reporting policy, and the
generated latch cells carry the ``always_latch`` attribute, which also
exempts them from `check` ``-nolatches``/``-latchonly``.
- The cell attribute ``wildcard_port_conns`` represents wildcard port - The cell attribute ``wildcard_port_conns`` represents wildcard port
connections (SystemVerilog ``.*``). These are resolved to concrete connections connections (SystemVerilog ``.*``). These are resolved to concrete connections