From 64d483442f96ff5c7c191c17daed4ec1ae74d997 Mon Sep 17 00:00:00 2001 From: nella Date: Tue, 14 Jul 2026 10:39:58 +0200 Subject: [PATCH] Document always_latch. --- docs/source/using_yosys/verilog.rst | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/docs/source/using_yosys/verilog.rst b/docs/source/using_yosys/verilog.rst index ef52bfc25..20f697cec 100644 --- a/docs/source/using_yosys/verilog.rst +++ b/docs/source/using_yosys/verilog.rst @@ -172,7 +172,10 @@ Verilog Attributes and non-standard features - The frontend sets attributes ``always_comb``, ``always_latch`` and ``always_ff`` on processes derived from SystemVerilog style always blocks according to the type of the always. These are checked for correctness in - ``proc_dlatch``. + ``proc_dlatch``. Latches inferred from ``always_latch`` processes are exempt + from the ``proc -latches `` reporting policy, and the + generated latch cells carry the ``always_latch`` attribute, which also + exempts them from `check` ``-nolatches``/``-latchonly``. - The cell attribute ``wildcard_port_conns`` represents wildcard port connections (SystemVerilog ``.*``). These are resolved to concrete connections