diff --git a/passes/techmap/abc_new.cc b/passes/techmap/abc_new.cc
index 477a46134..f8df67b39 100644
--- a/passes/techmap/abc_new.cc
+++ b/passes/techmap/abc_new.cc
@@ -191,13 +191,11 @@ struct AbcNewPass : public ScriptPass {
 				}
 
 				run(stringf("  abc9_ops -write_box %s/input.box", tmpdir));
-				run(stringf("  debug write_xaiger2 -mapping_prep -map2 %s/input.map2 %s/input.xaig", tmpdir, tmpdir));
+				run(stringf("  write_xaiger2 -mapping_prep -map2 %s/input.map2 %s/input.xaig", tmpdir, tmpdir));
 				run(stringf("  abc9_exe %s -cwd %s -box %s/input.box", exe_options, tmpdir, tmpdir));
 				run(stringf("  read_aiger -xaiger -module_name %s$abc9 %s/output.aig",
 							modname, tmpdir));
-				run(stringf("  debug abc_ops_reintegrate -map %s/input.map2", tmpdir));
-				//run(stringf("  debug read_xaiger2 -sc_mapping -module_name %s -map2 %s/input.map2 %s/output.aig",
-				//			modname, tmpdir, tmpdir));
+				run(stringf("  abc_ops_reintegrate -map %s/input.map2", tmpdir));
 				if (!help_mode && mod->has_attribute(ID(abc9_script))) {
 					if (script_save.empty())
 						active_design->scratchpad_unset("abc9.script");
diff --git a/passes/techmap/abc_ops_reintegrate.cc b/passes/techmap/abc_ops_reintegrate.cc
index 1e3f6681a..79084cdaa 100644
--- a/passes/techmap/abc_ops_reintegrate.cc
+++ b/passes/techmap/abc_ops_reintegrate.cc
@@ -551,11 +551,6 @@ void reintegrate(RTLIL::Module *module, bool dff_mode, std::string map_filename)
 	for (auto port : mapped_mod->ports) {
 		RTLIL::Wire *mapped_wire = mapped_mod->wire(port);
 		RTLIL::Wire *wire = module->wire(port);
-
-		if (!wire) {
-			log_debug("looking for port %s\n", port);
-			continue;
-		}
 		log_assert(wire);
 
 		RTLIL::Wire *remap_wire = module->wire(remap_name(port));
diff --git a/techlibs/gatemate/synth_gatemate.cc b/techlibs/gatemate/synth_gatemate.cc
index 4f2b27d4e..aa002c272 100644
--- a/techlibs/gatemate/synth_gatemate.cc
+++ b/techlibs/gatemate/synth_gatemate.cc
@@ -332,7 +332,7 @@ struct SynthGateMatePass : public ScriptPass
 					abc_args += " -dff";
 				}
 				if (abc_new) {
-					run("abc_new -nocleanup " + abc_args, "(with -luttree and -abc_new)");
+					run("abc_new " + abc_args, "(with -luttree and -abc_new)");
 				} else {
 					run("abc " + abc_args, "(with -luttree, without -abc_new)");
 				}
diff --git a/tests/arch/ice40/fsm.ys b/tests/arch/ice40/fsm.ys
index 2c2a9107d..b01d34bba 100644
--- a/tests/arch/ice40/fsm.ys
+++ b/tests/arch/ice40/fsm.ys
@@ -1,5 +1,3 @@
-scratchpad -set abc9.nocleanup 1
-
 read_verilog ../common/fsm.v
 hierarchy -top fsm
 proc
diff --git a/tests/techmap/xaiger2-5169.ys b/tests/techmap/xaiger2-5169.ys
index 1678d56ac..6f841088b 100644
--- a/tests/techmap/xaiger2-5169.ys
+++ b/tests/techmap/xaiger2-5169.ys
@@ -56,5 +56,5 @@ endmodule
 
 EOF
 
-logger -expect error "Malformed design" 1
+logger -expect error "Cannot find existing box cell" 1
 abc_new -liberty ../../tests/liberty/normal.lib -liberty ../../tests/liberty/dff.lib