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proc_dff: better error context 

(cherry picked from commit 404ce980e4)
This commit is contained in:
Emil J. Tywoniak 2026-02-09 19:02:51 +01:00
parent 0e30f20be3
commit 58f95dbab8
1 changed files with 21 additions and 6 deletions
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27
passes/proc/proc_dff.cc
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@ -169,6 +169,20 @@ void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_rst, RT
log(".\n"); log(".\n");
} }
template <typename T>
static void error_at_src(const RTLIL::Design* design, TwineRef src, T msg) {
if (src == Twine::Null) {
log_error("%s\n", msg);
} else {
log_error("%s: %s\n", design->twines.str(src).c_str(), msg);
}
}
template <typename T>
static void error_at_proc(const RTLIL::Process* proc, T msg) {
error_at_src(proc->module->design, proc->src_id(), msg);
}
void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
{ {
while (1) while (1)
@ -206,14 +220,15 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
async_rules.emplace_back(rstval, sync); async_rules.emplace_back(rstval, sync);
} }
else if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn) { else if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn) {
if (sync_edge != NULL && sync_edge != sync) if (sync_edge != NULL && sync_edge != sync) {
log_error("Multiple edge sensitive events found for this signal!\n"); error_at_src(mod->design, action.src, stringf("Multiple edge sensitive events found for signal %s", log_signal(sig)));
}
sig.replace(action.lhs, action.rhs, &insig); sig.replace(action.lhs, action.rhs, &insig);
sync_edge = sync; sync_edge = sync;
} }
else if (sync->type == RTLIL::SyncType::STa) { else if (sync->type == RTLIL::SyncType::STa) {
if (sync_always != NULL && sync_always != sync) if (sync_always != NULL && sync_always != sync)
log_error("Multiple always events found for this signal!\n"); error_at_proc(proc, stringf("Multiple always events found for signal %s", log_signal(sig)));
sig.replace(action.lhs, action.rhs, &insig); sig.replace(action.lhs, action.rhs, &insig);
sync_always = sync; sync_always = sync;
} }
@ -222,7 +237,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
global_clock = true; global_clock = true;
} }
else { else {
log_error("Event with any-edge sensitivity found for this signal!\n"); error_at_proc(proc, stringf("Event with any-edge sensitivity found for signal %s", log_signal(sig)));
} }
action.lhs.remove2(sig, &action.rhs); action.lhs.remove2(sig, &action.rhs);
@ -273,14 +288,14 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
if (sync_always) { if (sync_always) {
if (sync_edge || !async_rules.empty()) if (sync_edge || !async_rules.empty())
log_error("Mixed always event with edge and/or level sensitive events!\n"); error_at_proc(proc, stringf("Mixed always event with edge and/or level sensitive events for signal %s", log_signal(sig)));
log(" created direct connection (no actual register cell created).\n"); log(" created direct connection (no actual register cell created).\n");
mod->connect(RTLIL::SigSig(sig, insig)); mod->connect(RTLIL::SigSig(sig, insig));
continue; continue;
} }
if (!sync_edge && !global_clock) if (!sync_edge && !global_clock)
log_error("Missing edge-sensitive event for this signal!\n"); error_at_proc(proc, stringf("Missing edge-sensitive event for signal %s", log_signal(sig)));
// More than one reset value so we derive a dffsr formulation // More than one reset value so we derive a dffsr formulation
if (async_rules.size() > 1) if (async_rules.size() > 1)