mirror of https://github.com/YosysHQ/yosys.git
proc_mux: include switch expression location in $eq src
(cherry picked from commit 383daa1eb3)
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4985df71cb
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0e30f20be3
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@ -242,8 +242,13 @@ struct MuxGenCtx {
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// create compare cell
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RTLIL::Cell *eq_cell = mod->addCell(mod->design->twines.add(std::string{stringf("%s_CMP%d", sstr.str(), cmp_wire->width)}), ifxmode ? TW($eqx) : TW($eq));
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apply_attrs(eq_cell, cs);
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if (cs->compare_src != Twine::Null)
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eq_cell->set_src_attribute(cs->compare_src);
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std::vector<TwineRef> eq_sources;
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if (sw->signal_src != Twine::Null)
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eq_sources.push_back(sw->signal_src);
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if (cs->compare_src != Twine::Null && cs->compare_src != sw->signal_src)
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eq_sources.push_back(cs->compare_src);
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if (!eq_sources.empty())
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eq_cell->set_src_attribute(mod->design->twines.concat(std::span<const TwineRef>{eq_sources}));
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eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
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eq_cell->parameters[ID::B_SIGNED] = RTLIL::Const(0);
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@ -1,10 +1,10 @@
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read_verilog proc_mux_src.v
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proc -noopt
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check -assert
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# eq refer to the values compared against
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# eq refer to both sides of the comparison of switch signal vs case value
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select -assert-count 2 tiny2/t:$eq
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select -assert-count 1 tiny2/t:$eq a:src=proc_mux_src.v:81.4-81.10 %i
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select -assert-count 1 tiny2/t:$eq a:src=proc_mux_src.v:84.4-84.10 %i
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select -assert-count 1 tiny2/t:$eq a:src=proc_mux_src.v:80.9-80.11|proc_mux_src.v:81.4-81.10 %i
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select -assert-count 1 tiny2/t:$eq a:src=proc_mux_src.v:80.9-80.11|proc_mux_src.v:84.4-84.10 %i
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# Flops cover the assigned to wire and whole process
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select -assert-count 1 tiny2/t:$dff
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select -assert-count 1 tiny2/t:$dff a:src=proc_mux_src.v:76.19-76.22|proc_mux_src.v:78.2-91.5
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