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Prepare dff_mode
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@ -2429,18 +2429,6 @@ struct AbcPass : public Pass {
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sig2src[bit] = bit.wire->get_src_attribute();
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}
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if (!dff_mode || !clk_str.empty()) {
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std::vector<RTLIL::Cell*> cells = mod->selected_cells();
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assign_cell_connection_ports(mod, {&cells}, assign_map);
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AbcModuleState state(config, initvals, 0);
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state.prepare_module(design, mod, assign_map, cells, dff_mode, clk_str);
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ConcurrentStack<AbcProcess> process_pool;
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state.run_abc.run(process_pool);
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state.extract(assign_map, sig2src, sigmap, design, mod);
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continue;
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}
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CellTypes ct(design);
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std::vector<RTLIL::Cell*> all_cells = mod->selected_cells();
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