From 4758019cc7f50ac8459ed4b8506b0af137ebeda5 Mon Sep 17 00:00:00 2001
From: Akash Levy <akash@silimate.com>
Date: Thu, 6 Nov 2025 17:05:02 -0800
Subject: [PATCH] Prepare dff_mode

---
 passes/techmap/abc.cc | 12 ------------
 1 file changed, 12 deletions(-)

diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 5e1cf6d86..6e41b627f 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -2429,18 +2429,6 @@ struct AbcPass : public Pass {
 								sig2src[bit] = bit.wire->get_src_attribute();
 						}
 
-			if (!dff_mode || !clk_str.empty()) {
-				std::vector<RTLIL::Cell*> cells = mod->selected_cells();
-				assign_cell_connection_ports(mod, {&cells}, assign_map);
-
-				AbcModuleState state(config, initvals, 0);
-				state.prepare_module(design, mod, assign_map, cells, dff_mode, clk_str);
-				ConcurrentStack<AbcProcess> process_pool;
-				state.run_abc.run(process_pool);
-				state.extract(assign_map, sig2src, sigmap, design, mod);
-				continue;
-			}
-
 			CellTypes ct(design);
 
 			std::vector<RTLIL::Cell*> all_cells = mod->selected_cells();