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Merge pull request #6078 from YosysHQ/emil/hierarchy-fix-keep-cache 

hierarchy: fix keep cache usage by caching false too
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Emil J 2026-08-03 15:54:50 +00:00 committed by GitHub
parent 0955fcadab a27378cff8
commit 468ba27d91
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GPG Key ID: B5690EEEBB952194
3 changed files with 48 additions and 14 deletions
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34
passes/hierarchy/hierarchy.cc
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@ -684,24 +684,30 @@ void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib)
bool set_keep_print(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod) bool set_keep_print(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
{ {
if (cache.count(mod) == 0) auto it = cache.find(mod);
for (auto c : mod->cells()) { if (it != cache.end())
RTLIL::Module *m = mod->design->module(c->type); return it->second;
if ((m != nullptr && set_keep_print(cache, m)) || c->type == ID($print)) cache[mod] = false;
return cache[mod] = true; for (auto c : mod->cells()) {
} RTLIL::Module *m = mod->design->module(c->type);
return cache[mod]; if ((m != nullptr && set_keep_print(cache, m)) || c->type == ID($print))
return cache[mod] = true;
}
return false;
} }
bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod) bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
{ {
if (cache.count(mod) == 0) auto it = cache.find(mod);
for (auto c : mod->cells()) { if (it != cache.end())
RTLIL::Module *m = mod->design->module(c->type); return it->second;
if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in(ID($check), ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) cache[mod] = false;
return cache[mod] = true; for (auto c : mod->cells()) {
} RTLIL::Module *m = mod->design->module(c->type);
return cache[mod]; if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in(ID($check), ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))
return cache[mod] = true;
}
return false;
} }
int find_top_mod_score(Design *design, Module *module, dict<Module*, int> &db) int find_top_mod_score(Design *design, Module *module, dict<Module*, int> &db)

3
tests/various/hierarchy_recursive.v Normal file
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@ -0,0 +1,3 @@
module top(input x, output y);
top top_i(.x(x), .y(y));
endmodule

25
tests/various/hierarchy_recursive.ys Normal file
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@ -0,0 +1,25 @@
read_verilog hierarchy_recursive.v
hierarchy -auto-top
select -assert-any top
select -assert-none a:keep
design -reset
read_verilog <<EOT
module top(input x, output y);
top top_i(.x(x), .y(y));
always @(x) $display("x=%d", x);
endmodule
EOT
hierarchy -auto-top
select -assert-any top %% a:keep
design -reset
read_verilog -formal <<EOT
module a(input x); b b_i(.x(x)); endmodule
module b(input x); a a_i(.x(x)); always @(x) assert (x == x); endmodule
module top(input x); a a_i(.x(x)); endmodule
EOT
hierarchy -top top
select -assert-any a %% a:keep
select -assert-any b %% a:keep
select -assert-any top %% a:keep