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wreduce: fixup initvals after setPort

This commit is contained in:
Emil J. Tywoniak 2026-03-10 14:01:57 +01:00
parent b0c3f3ea00
commit 42a75ffda9
1 changed files with 9 additions and 1 deletions
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10
passes/opt/wreduce.cc
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@ -147,7 +147,8 @@ struct WreduceWorker
SigSpec sig_d = mi.sigmap(cell->getPort(ID::D)); SigSpec sig_d = mi.sigmap(cell->getPort(ID::D));
SigSpec sig_q = mi.sigmap(cell->getPort(ID::Q)); SigSpec sig_q = mi.sigmap(cell->getPort(ID::Q));
bool has_reset = false; bool has_reset = false;
Const initval = initvals(sig_q), rst_value; Const rst_value;
std::vector<State> initval = initvals(sig_q).to_bits();
int width_before = GetSize(sig_q); int width_before = GetSize(sig_q);
@ -165,12 +166,16 @@ struct WreduceWorker
bool zero_ext = sig_d[GetSize(sig_d)-1] == State::S0; bool zero_ext = sig_d[GetSize(sig_d)-1] == State::S0;
bool sign_ext = !zero_ext; bool sign_ext = !zero_ext;
if (mi.auto_reload_module)
mi.reload_module();
for (int i = GetSize(sig_q)-1; i >= 0; i--) for (int i = GetSize(sig_q)-1; i >= 0; i--)
{ {
if (zero_ext && sig_d[i] == State::S0 && (initval[i] == State::S0 || (!config->keepdc && initval[i] == State::Sx)) && if (zero_ext && sig_d[i] == State::S0 && (initval[i] == State::S0 || (!config->keepdc && initval[i] == State::Sx)) &&
(!has_reset || i >= GetSize(rst_value) || rst_value[i] == State::S0 || (!config->keepdc && rst_value[i] == State::Sx))) { (!has_reset || i >= GetSize(rst_value) || rst_value[i] == State::S0 || (!config->keepdc && rst_value[i] == State::Sx))) {
module->connect(sig_q[i], State::S0); module->connect(sig_q[i], State::S0);
initvals.remove_init(sig_q[i]); initvals.remove_init(sig_q[i]);
initval.erase(initval.begin() + i);
sig_d.remove(i); sig_d.remove(i);
sig_q.remove(i); sig_q.remove(i);
continue; continue;
@ -180,6 +185,7 @@ struct WreduceWorker
(!has_reset || i >= GetSize(rst_value) || (rst_value[i] == rst_value[i-1] && (!config->keepdc || rst_value[i] != State::Sx)))) { (!has_reset || i >= GetSize(rst_value) || (rst_value[i] == rst_value[i-1] && (!config->keepdc || rst_value[i] != State::Sx)))) {
module->connect(sig_q[i], sig_q[i-1]); module->connect(sig_q[i], sig_q[i-1]);
initvals.remove_init(sig_q[i]); initvals.remove_init(sig_q[i]);
initval.erase(initval.begin() + i);
sig_d.remove(i); sig_d.remove(i);
sig_q.remove(i); sig_q.remove(i);
continue; continue;
@ -190,6 +196,7 @@ struct WreduceWorker
return; return;
if (!info->is_output && GetSize(info->ports) == 1 && !keep_bits.count(mi.sigmap(sig_q[i]))) { if (!info->is_output && GetSize(info->ports) == 1 && !keep_bits.count(mi.sigmap(sig_q[i]))) {
initvals.remove_init(sig_q[i]); initvals.remove_init(sig_q[i]);
initval.erase(initval.begin() + i);
sig_d.remove(i); sig_d.remove(i);
sig_q.remove(i); sig_q.remove(i);
zero_ext = false; zero_ext = false;
@ -229,6 +236,7 @@ struct WreduceWorker
cell->setPort(ID::D, sig_d); cell->setPort(ID::D, sig_d);
cell->setPort(ID::Q, sig_q); cell->setPort(ID::Q, sig_q);
initvals.set_init(cell->getPort(ID::Q), initval);
cell->fixup_parameters(); cell->fixup_parameters();
} }