mirror of https://github.com/YosysHQ/yosys.git
ff: fixup initvals with signorm direct drive wire if it's created, not old driven wire
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@ -635,8 +635,6 @@ Cell *FfData::emit() {
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return nullptr;
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}
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}
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if (initvals && !is_anyinit)
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initvals->set_init(sig_q, val_init);
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if (!is_fine) {
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if (has_gclk) {
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log_assert(!has_clk);
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@ -747,6 +745,8 @@ Cell *FfData::emit() {
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}
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}
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cell->attributes = attributes;
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if (initvals && !is_anyinit)
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initvals->set_init(cell->getPort(ID::Q), val_init);
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return cell;
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}
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