mirror of
https://github.com/YosysHQ/yosys.git
synced 2026-09-07 12:21:16 +02:00
spinner and pre-load files
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+43
-14
@@ -44,7 +44,11 @@ bool ColorLogSink::should_log(const LogMessage &msg) const
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return true;
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else
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return (msg.severity == LogSeverity::Warning || msg.severity == LogSeverity::Error);
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//return (msg.severity == LogSeverity::Warning || msg.severity == LogSeverity::Error || msg.severity == LogSeverity::Header);
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}
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//static constexpr std::array<std::string_view, 4> spinner = { "-", "\\", "|", "/" };
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//static int counter = 0;
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void ColorLogSink::log(const LogMessage &msg)
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{
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FILE *f = stderr;
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@@ -60,6 +64,7 @@ void ColorLogSink::log(const LogMessage &msg)
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break;
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case LogSeverity::Header:
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//fmt::print(f,"\r\x1b[2K[{}] Processing...", spinner[counter++ % 4]); fflush(f);
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fmt::print(f, fg(fmt::terminal_color::cyan) | fmt::emphasis::bold, "{}", msg.prefix);
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fmt::print(f, fg(fmt::terminal_color::white) | fmt::emphasis::bold, "{}", msg.message);
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break;
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@@ -167,6 +172,7 @@ public:
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std::string name;
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std::string description;
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std::vector<std::string> passes;
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std::vector<std::string> files;
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};
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using SourceStandard = std::variant<
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VerilogStandard,
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@@ -188,7 +194,7 @@ public:
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VerilogStandard verilog_standard = VerilogStandard::Latest;
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SystemVerilogStandard system_verilog_standard = SystemVerilogStandard::Latest;
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VhdlStandard vhdl_standard = VhdlStandard::Latest;
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SystemVerilogFrontend system_verilog_frontend = SystemVerilogFrontend::Slang;
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SystemVerilogFrontend system_verilog_frontend = SystemVerilogFrontend::Legacy;
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VhdlFrontend vhdl_frontend;
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void addStandardArgs();
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@@ -198,12 +204,14 @@ public:
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void printOption(const std::string& name, const std::string& desc);
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void registerTarget(std::string name,
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std::string description,
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std::vector<std::string> passes)
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std::vector<std::string> passes,
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std::vector<std::string> files)
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{
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targets.push_back({
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std::move(name),
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std::move(description),
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std::move(passes)
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std::move(passes),
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std::move(files)
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});
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}
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};
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@@ -248,9 +256,9 @@ int YosysDriver::run(int argc, char **argv) {
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log_error_atexit = &yc_error_atexit;
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logger().add_sink<ColorLogSink>();
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registerTarget("ice40", "Lattice iCE 40", {"synth_ice40"});
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registerTarget("ecp5", "Lattice ECP5", {"synth_ecp5"});
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registerTarget("gatemate", "GateMate A1", {"synth_gatemate"});
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registerTarget("ice40", "Lattice iCE40", {"synth_ice40"}, { "+/ice40/cells_sim.v"});
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registerTarget("ecp5", "Lattice ECP5", {"synth_ecp5"}, { "+/ecp5/cells_sim.v", "+/ecp5/cells_bb.v"});
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registerTarget("gatemate", "GateMate A1", {"synth_gatemate"}, { "+/gatemate/cells_sim.v", "+/gatemate/cells_bb.v"});
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cmdLine.add("-h,--help", options.showHelp, "Display available options");
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cmdLine.add("--version", options.showVersion, "Display version information and exit");
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@@ -542,7 +550,6 @@ int YosysDriver::run(int argc, char **argv) {
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show_build_status = true;
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std::vector<std::string> passes;
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passes.push_back("read -noverific");
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if (!options.defines.empty()) {
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for (auto vdef : options.defines) {
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switch (system_verilog_frontend)
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@@ -567,10 +574,36 @@ int YosysDriver::run(int argc, char **argv) {
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passes.push_back("read -undef " + vdef);
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}
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//for (auto fn : sourceFiles)
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//passes.push_back(stringf("read_verilog -sv %s", fn));
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//run_frontend(fn.c_str(), "auto");
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auto it = std::find_if(targets.begin(), targets.end(),
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[this](const auto &target) {
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return target.name == options.target;
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});
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std::string files;
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for (const auto &f : it->files) {
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std::string fn = f;
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rewrite_filename(fn);
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if (!files.empty())
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files += ' ';
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files += fn;
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}
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switch (system_verilog_frontend)
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{
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case SystemVerilogFrontend::Legacy:
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passes.push_back(stringf("read_verilog -lib -specify %s", files));
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break;
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case SystemVerilogFrontend::Slang:
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passes.push_back(stringf("read_slang %s", files));
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break;
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case SystemVerilogFrontend::Verific:
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passes.push_back(stringf("verific -vlog-incdir -I /home/micko/src/yosys/build/share/ecp5"));
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passes.push_back(stringf("verific -sv -lib %s ", files));
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break;
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}
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for (const auto &file : sourceFiles)
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{
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@@ -631,10 +664,6 @@ int YosysDriver::run(int argc, char **argv) {
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passes.push_back(stringf("hierarchy -top %s", options.topModule.value()));
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//passes.push_back(stringf("synth_%s", options.target.value()));
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auto it = std::find_if(targets.begin(), targets.end(),
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[this](const auto &target) {
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return target.name == options.target;
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});
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for (const auto &pass : it->passes) {
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// run pass
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