From 414c9e8898f2c5f98bc09603c414edfc7fbf20c5 Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Wed, 25 Jun 2025 22:09:43 -0700 Subject: [PATCH] Fix annotate_cell_fanout issue by double uniquifying... hopefully should fix the issue? --- passes/silimate/annotate_cell_fanout.cc | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/passes/silimate/annotate_cell_fanout.cc b/passes/silimate/annotate_cell_fanout.cc index 5dec6f5c1..8cbb4a7c8 100644 --- a/passes/silimate/annotate_cell_fanout.cc +++ b/passes/silimate/annotate_cell_fanout.cc @@ -346,11 +346,13 @@ void fixfanout(RTLIL::Module *module, SigMap &sigmap, dict> buffer_chunk_outputs; for (int i = 0; i < num_buffers; ++i) { - std::string wireName = generateSigSpecName(module, sigToBuffer, "_wbuf", index_buffer).c_str(); - std::string cellName = generateSigSpecName(module, sigToBuffer, "_fbuf", index_buffer).c_str(); + RTLIL::IdString wireName = generateSigSpecName(module, sigToBuffer, "_wbuf", index_buffer); + RTLIL::IdString cellName = generateSigSpecName(module, sigToBuffer, "_fbuf", index_buffer); RTLIL::Cell *buffer = module->addCell(cellName, ID($buf)); bufferActualFanout[buffer] = 0; - RTLIL::SigSpec buffer_output = module->addWire(wireName, chunk.size()); + if (module->count_id(wireName) != 0) + log_warning("Wire name %s already exists somehow...\n", wireName.c_str()); + RTLIL::SigSpec buffer_output = module->addWire(module->uniquify(wireName), chunk.size()); insertedBuffers.emplace(buffer, buffer_output.as_wire()); buffer->setPort(ID(A), chunk); buffer->setPort(ID(Y), sigmap(buffer_output));