Merge pull request #6220 from YosysHQ/nella/portarcs-zero-delay

portarcs: avoid dividing by zero with zero delays

passes/cmds/portarcs.cc

@@ -262,6 +262,9 @@ struct PortarcsPass : Pass {
 							max_delay = p[i];
 				}
 
+				if (max_delay == 0)
+					max_delay = 1;
+
 				log("Delay legend:\n\n");
 				log("    ");
 				for (int i = 0; i < 24; i++)

tests/abc_new/generate_mk.py

@@ -11,7 +11,6 @@ skip = [
     "hier_check.ys",
     "keep_wire.ys",
     "scopeinfo.ys",
-    "whitebox_portarcs_fpe.ys",
 ]
 
 def create_tests():

tests/abc_new/whitebox_equiv.ys

@@ -1,4 +1,4 @@
-# lib_whitebox mux box mapped itself, then used as timing box (needs -unit_delay, see whitebox_portarcs_fpe.ys)
+# lib_whitebox mux box mapped itself, then used as timing box (needs -unit_delay, see whitebox_no_timing.ys)
 read_verilog -specify <<EOT
 (* abc9_box, lib_whitebox *)
 module MX4(input D0, D1, D2, D3, S0, S1, output Y);

tests/abc_new/whitebox_no_timing.ys

@@ -1,4 +1,5 @@
-# mapped cells without timing: portarcs -draw divides by zero (portarcs.cc:285), SIGFPE
+# abc_new maps the box to cells without timing; prep_box must reject it, not crash
+logger -expect error "has no timing" 1
 read_verilog -specify <<EOT
 (* abc9_box, lib_whitebox *)
 module MX4(input D0, D1, D2, D3, S0, S1, output Y);