chores: run pre-commit for rest of rules

backends/verilog/verilog_backend.cc

@@ -677,7 +677,7 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem)
 				dump_sigspec(os, port.srst);
 				os << stringf(") begin\n");
 				clk_to_lof_body[clk_domain_str].push_back(os.str());
-				
+
 				std::ostringstream os2;
 				os2 << stringf("%s" "%s <= ", indent, temp_id);
 				dump_sigspec(os2, port.srst_value);

tests/techmap/abc_new.ys

@@ -10,4 +10,3 @@ EOT
 hierarchy -top top
 techmap
 abc_new -liberty ../liberty/normal.lib -liberty ../liberty/dff.lib
-

tests/techmap/dlatchlibmap_dlatchn.lib

@@ -4,7 +4,7 @@ library(test) {
     latch("IQ", "IQN") {
       data_in : "D";
       enable : "!ENA";
-    } 
+    }
     pin(D) {
       direction : input;
     }
@@ -18,6 +18,6 @@ library(test) {
     pin(QN) {
       direction: output;
       function : "IQN";
-    } 
+    }
   }
 }

tests/techmap/dlatchlibmap_dlatchsr_not_data.lib

@@ -24,4 +24,4 @@ library (test_not_data) {
       preset : "!RN";
     }
   }
-}
+}